Circuit arrangement for compensation for nonlinearities from...

Coded data generation or conversion – Converter compensation

Reexamination Certificate

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C341S138000, C341S141000, C341S155000, C341S159000

Reexamination Certificate

active

07135999

ABSTRACT:
A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlinearities (NL1, NL2) in the various analog/digital converters (15, 16) essentially compensate for one another.

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patent: 5973633 (1999-10-01), Hester
patent: 6452518 (2002-09-01), Kawabata
patent: 6522282 (2003-02-01), Elbornsson

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