Circuit arrangement for coding or decoding of binary data

Details Circuit arrangement for coding or decoding of binary data Circuit arrangement for coding or decoding of binary data

1978-12-19

1980-12-30

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

042427525

ABSTRACT:
The invention relates to a circuit arrangement for coding or decoding wherein check bits are formed using a cyclic code, in which an information polynomial is divided by a generator polynomial. The coding permits adaptation to the checking requirements in the simplest manner. The invention provides apparatus for dividing the binary information into a plurality of words of equal bit numbers, a modulo-2-adder, and a partial decoder. The partial decoder divides the words by the generator polynomial and the remainder determined is added to the next word in the modulo-2-adder. The partial coder can be an ROM. The circuit arrangement is particularly suitable for utilization in telecontrol installations.

REFERENCES:
patent: 3452328 (1969-06-01), Hsiao et al.
patent: 3678469 (1972-07-01), Freeman et al.
patent: 3703705 (1972-11-01), Patel
patent: 4105999 (1978-08-01), Nakamura
patent: 4107650 (1978-08-01), Luke et al.
"Pocket Guide", Texas Instruments, Sep. 1976, p. 296.
MC 5-86, User's Manual, Intel Corp., Jun. 1977, p. 41.

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