Multiplex communications – Wide area network – Packet switching
Patent
1990-11-13
1993-05-11
Chin, Wellington
Multiplex communications
Wide area network
Packet switching
375118, 307269, 331172, H04J 306, H04L 702
Patent
active
052107558
ABSTRACT:
Line terminal groups are redundantly present for reliability reasons. The connecting through of the input lines to the switching matrix network can thereby proceed via different signal paths. In order to avoid disturbances during switch-over between signal paths, the appertaining interfaces are provided with compensation memories. The data contained in the compensation memories are written in or read out in a phase-synchronized and frame-synchronized manner with a uniform clock. The uniform clock is acquired from the electronic switching device base clock of the system. Due to transient time distortions and component tolerances, the base clock must be regenerated with the circuit arrangement of the invention before it is applied to the compensation memories.
REFERENCES:
patent: 3808368 (1974-04-01), Pitroda et al.
patent: 4488292 (1984-12-01), Troost
patent: 4620312 (1986-10-01), Yamashita
patent: 5059818 (1991-10-01), Witt et al.
Nagler Werner
Schmidt Lothar
Chin Wellington
Siemens Aktiengesellschaft
LandOfFree
Circuit arrangement for clock regeneration in clock-controlled i does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit arrangement for clock regeneration in clock-controlled i, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for clock regeneration in clock-controlled i will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1356585