Circuit arrangement for channel-specific processing of a multi-c

Pulse or digital communications – Repeaters – Testing

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375 28, 370 60, 370 941, 370 99, 379202, 178 71R, H04B 1404, H04J 324

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active

051723930

ABSTRACT:
A circuit arrangement for channel-specific processing of a multi-channel input signal which may consist of two types of encoded signals, a first type wherein all channel signals are encoded by a bit-oriented method (e.g., delta modulation) and a second type wherein all channel signals are encoded by a character-oriented method (e.g., PCM). An interface process (SSP), to which the input signal is applied, is coupled to a bidirectional interface (BIS) for signals of the first type and which is controllable by means of write and read addresses, and is also coupled to at least two such bidirectionally controllable interfaces (BI0, BI1, . . . BI7) for signals of the second type. The latter interfaces are respectively coupled to respective transcoder processors (AP0, AP1, . . . AP7). One or more data outputs of the interface (BIS) for signals of the first type are respectively coupled to respective ones of the transcoder processors (AP0, AP1, . . . AP7). The transcoded channel signals produced by such processors are transmitted via the interfaces (BIS, BI0, . . . BI7) to the interface processor (SSP), which combines them into a multi-channel output signal.

REFERENCES:
patent: 4434485 (1984-02-01), Huffman et al.
patent: 4597074 (1986-06-01), Demichelis et al.
patent: 4797654 (1989-01-01), Young et al.

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