Circuit arrangement for calculating product sums

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364754, G06F 700, G06F 752

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051114224

ABSTRACT:
By using a basic cell (g), an overall array (ga) for forming n products from pairs of multidigit binary numbers Amn, Bkn and for adding these n products is formed, with the formation and summation of all partial products being interleaved row by row. Each basic cell contains a delay unit for the A-coefficient inputs controlled by a half clock signal, an undelayed through connection for the B-coefficient input, an added fed via respective delay units with a sum input, a carry input, and a summation input, and a logic gate which combines the B-coefficient with the undelayed A-coefficients to form the partial product thereof and provides the partial product to the summation input of the adder.

REFERENCES:
patent: 4573136 (1986-02-01), Rossiter
patent: 4679164 (1987-07-01), Renrich
IEE Proceedings-G/Electronic Circuits & Systems, Book 134, No. 5, Teil G., Oct., 1987, pp. 216-224, "Efficient Bit-Level Systolic Array for the Linear Discriminant Function Classifier".
Proceedings of the 7th Symposium on Computer Arithmetic, Jun, 1985 IEEE, New York, U.S.; S. P. Smith, et al., "Design of a fast Inner Product Processor" IEEE Trans. on Computers, Book C-29, No. 10, Oct., 1980, pp. 946-950, E. E. Swartzlander, Jr: Merged Arthmetic.

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