Boots – shoes – and leggings
Patent
1993-05-07
1995-06-06
Malzann, David H.
Boots, shoes, and leggings
364754, G06F 15347
Patent
active
054228360
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a circuit arrangement for calculating matrix operations which recur frequently, such as those in signal processing, especially in the context of neural networks. Since the computation operations which are required for calculating neural networks can be reduced to a comprehensible number of elementary matrix operations, it is sensible from the point of view of the necessary high computation speed in the execution of these operations to implement such computation operations in hardware, rather than to carry them out with the aid of software.
A prior art which is closest to the invention is reproduced in the publication by U. Ramacher, "Design of a first Generation Neurocomputer", VLSI Design of Neural Networks, edited by U. Ramacher, U. Ruckert, Kluwer Academic Publishers, Nov. 1990. This publication describes a circuit arrangement which is constructed from a systolic arrangement of multipliers and adders. This systolic arrangement makes it possible to calculate matrix products, the matrices which are to be multiplied being split into blocks of size 4.times.4, and it being possible to multiply submatrices of this size with the aid of the systolic arrangement in each case. The computation operations which can be carried out using this circuit arrangement are suitable for the calculation of specific neural network types, for example multilayer perceptron networks with feedback.
The disadvantages of this circuit arrangement, as it is described in the publication by U. Ramacher 1990, are primarily that:
the transposition, addition and subtraction are not supported by matrices,
result matrices cannot be squared or cannot be multiplied by a scalar, and that
the calculation of row and column sums and the search for extreme matrix elements are not supported by this circuit arrangement.
Furthermore, in the case of this circuit arrangement, there is no monitoring of the value range of the matrix coefficients, and the value ranges of the matrix elements are not limited if an overflow occurs.
SUMMARY OF THE INVENTION
The object on which the invention is based is to specify a circuit arrangement by means of which the described disadvantages of the prior art are overcome, and which supports the calculation of matrix products and the multiplication of matrix products by scalars, as well as the squaring of matrix products, sums and different formation of matrices, the multiplication of matrix sums and matrix differences by scalars, forming the magnitude of matrix sums and matrix differences, squaring matrix sums and matrix differences, transposition of matrices and matrix products, the calculation of row and column sums of matrices, and the search for extreme, that is to say minimum and maximum, matrix elements. This object is achieved by means of a circuit arrangement for calculating matrix operations, having a matrix multiplier and a recursive accumulator, which is connected downstream from this matrix multiplier, and having the following features:
the matrices which are to be processed by the circuit arrangement are partitioned into k x k submatrices;
the overall circuit has first and second inputs, one output and one input/output;
the matrix multiplier has the following units:
dual-port first and second memory units for the storage and transposition of input submatrices, the first memory unit being connected to the first input and the second memory unit being connected to the input/output, and the first memory unit having k independent memories;
a systolic arrangement, which is connected to the first and second memory units via inputs which are controlled by control signals, which arrangement has k multipliers and k downstream-connected adders for the multiplication and addition/subtraction of input submatrices, the first memory unit storing the rows of the submatrix in k separate sub-memory units, and supplying this data via k separate supply lines to the multipliers, so that each multiplier, with the downstream-connected adder successively, and in a synchronized
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Beichter Jorg
Ramacher Ulrich
Malzann David H.
Siemens Aktiengesellschaft
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