Circuit arrangement for bit rate adjustment to two digital signa

Details Circuit arrangement for bit rate adjustment to two digital signa Circuit arrangement for bit rate adjustment to two digital signa

1993-06-18

1994-07-19

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

370102, H04L 2536

Patent

active

053316711

ABSTRACT:
A buffer memory, in which a first signal is written and from which a second signal is read out, and a subtractor which forms the difference between the counts of a read counter and a write counter, which control reading and writing. A justification decision circuit generates a stop signal for the read counter. An accumulator accumulates the difference signal over a predetermined time interval. The accumulator output, delayed by a time interval and weighted with a second factor, and a justification signal denoting the number of stuff bits caused by the justification decision circuit between two stop instants, are added to the subtractor output in the accumulator.

REFERENCES:
patent: 4002844 (1977-01-01), Doussoux
patent: 4352181 (1982-09-01), Le Dieu et al.
patent: 4667324 (1987-05-01), Graves
patent: 4731646 (1988-03-01), Kliem
patent: 4928275 (1990-05-01), Moore et al.

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