Multiplex communications – Wide area network – Packet switching
Patent
1990-12-17
1993-11-09
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
375118, 377 39, H04J 307
Patent
active
052609405
ABSTRACT:
A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18). The phase comparator (16) compares the count of the balancing counter (14 ) to the count of the read address counter (8) and the output signal of the phase comparator (16) is used for producing the clock for the read address counter (8).
REFERENCES:
patent: 4764942 (1988-08-01), Shigaki et al.
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.
Barschall Anne E.
Jung Min
Olms Douglas W.
U.S. Philips Corporation
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