Circuit arrangement for bit rate adaptation

Details Circuit arrangement for bit rate adaptation Circuit arrangement for bit rate adaptation

1992-12-18

1994-07-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701053, 370108, 375118, H04J 306

Patent

active

053274300

ABSTRACT:
A circuit arrangement for adapting the bit rates of two signals to each other comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7, 8). In order to largely avoid jitter in the signal that has been read, the read address counter (8) and the phase comparator (16) are incorporated in a control circuit that controls the clock for the read address counter (8). In this control circuit the output signal of the phase comparator (16) is the control error. The controlled system (17) of the control circuit consists of a controllable oscillator circuit with whose output signal and read address counter (8) is clocked. In order to avoid stationary phase shifts with a constant frequency shift, a controller (18) having a PI behavior (PI=proportionality and integration) is used.

REFERENCES:
patent: 4072826 (1978-02-01), Aveneau
patent: 4224481 (1980-09-01), Russell
patent: 4764942 (1988-08-01), Shigaki et al.
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4888564 (1989-12-01), Ishigaki
patent: 4928275 (1990-05-01), Moore et al.
"The Art of Electronics", (2nd Ed.), published by Cambridge University Press, 1989, pp. 641, 644 and 647.

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