Circuit arrangement for bit rate adaptation

Details Circuit arrangement for bit rate adaptation Circuit arrangement for bit rate adaptation

1990-12-17

1993-03-16

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375118, 3701053, 331 1A, 377 39, H04J 306

Patent

active

051950880

ABSTRACT:
A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock. In order to prevent stationary phase shifts from producing a constant frequency shift of the oscillator, the control circuit provides a PI behavior (proportionality and integration) of the frequency control signal supplied to the oscillator.

REFERENCES:
patent: 4072826 (1978-02-01), Aveneau
patent: 4224481 (1980-09-01), Russell
patent: 4574254 (1986-03-01), Glance
patent: 4731646 (1988-03-01), Kliem
patent: 4764942 (1988-08-01), Shigaki et al.
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4888564 (1989-12-01), Ishigaki
patent: 4928275 (1990-05-01), Moore et al.

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