Circuit arrangement for averaging signals during pulse-density D

Details Circuit arrangement for averaging signals during pulse-density D Circuit arrangement for averaging signals during pulse-density D

1989-03-10

1990-08-07

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

341126, 375 23, H03M 100

Patent

active

049471716

ABSTRACT:
In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.

REFERENCES:
patent: 4125803 (1978-11-01), Van de Plassche
patent: 4156871 (1979-05-01), Lambourn
patent: 4366572 (1982-12-01), Takatsuki et al.
patent: 4559602 (1985-12-01), Bates
patent: 4712217 (1987-12-01), McPherson
patent: 4825452 (1989-04-01), Wong
Heinrich Pfeifer, "Analog/Digital-Umsetzung mit einem Pulsdichtemodulator," (Analog/Digital-Conversion with a Pulse-density Modulator), Elektronik, No. 19, Sep. 20, 1985, pp. 75 to 77.
H. Deutsch, et al., "Digital Filter for Delta Demodulation," IBM Technical Disclosure Bulletin, vol. 10, No. 4, Sep. 1967, p. 370.
European Search Report, Application No. 88105242.7, Oct. 27, 1988.

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