Circuit arrangement for adding or subtracting operands coded in

Details Circuit arrangement for adding or subtracting operands coded in Circuit arrangement for adding or subtracting operands coded in

1990-12-07

1992-09-08

Nguyen, Long T.

Boots, shoes, and leggings

G06F 750

Patent

active

051464233

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to a circuit arrangement for adding or subtracting operands coded in BCD-code or binary-code upon employment of a binary adder.
Up to now, different circuit arrangements have been proposed for adding or subtracting operands coded in binary code or BCD code. Given additions or subtractions of operands in the binary code, a circuit for generating a one's or a two's complement was thereby necessary. Given BCD operands, by contrast, a circuit for generating the nine's complement was required.
Binary adders are known (see, for example, U. Tietze, Ch. Schenk, Halbleiterschaltungstechnik, 4th Edition, Springer Verlag, Berlin Heidelberg New York, 1978, pages 475, 476). It is also known to add or subtract BCD numbers upon employment of binary adders. Two binary adders, however, are required for this purpose. (See op. cit., page 477). The second binary adder is required in order to correct the result of the first binary adder. This is necessary when a carry occurs in a decade. A 6 must then be added to the result of the first binary adder. This BCD number, however, can contain a pseudo-tetrade. In this case, the number 6 must still be added in order to eliminate the pseudo-tetrade. The correction of the result of the first binary adder ensues with the assistance of the second binary adder. The overall outlay for the circuit arrangement for adding PCD numbers is thus relatively great and the circuit works relatively slowly.


SUMMARY OF THE INVENTION

The object on which the invention is based is comprised in specifying a circuit arrangement of the species initially set forth that edits a 4-bit-wide datum of an operand such that both binary as well as BCD additions and subtractions can be implemented with a single binary adder.
This object is achieved by a circuit arrangement for adding or subtracting 4-bit first and second operands coded in one of BCD-code or binary code upon employment of a binary added, comprising: a first input stage connected preceding a first input of the binary adder for receiving the first operand, said first input stage adding the number 6 to said first operand given operations of BVD operands with positive operands; adding the number 6 to said first operand given negative operands and negating the result; not modifying said operand given different operational signals of the two operands and positive operational sign of said first operand; negating said first operand given different operational signs of the two operands given negative operational signal of said first operand; negating said first operand but not otherwise modifying it given operations of operands in the binary code with a negative said first operand; a second input stage, that, receiving a negative, second operand, negates this but otherwise leaves it unmodified, connected preceding a second input of the binary adder; an output stage connected to a sum output of the binary adder, said output stage given BCD operations of the first and second operands and non-presence of a carry on a carry output of the binary adder, subtracting the number 6 from a sum result on the sum output of the binary adder in order to generate a corrected sum but otherwise not influencing the sum result.
The number 6 is added to one of the operands when required given binary additions or, respectively, subtractions, being added with the assistance of input stages that are switched by the binary adders. This is valid when a BCD addition is present and both operands are positive or negative. When only one of the operands is negative, then this operand is negated. By contrast, the input stages handle binary numbers such that they are only modified when the operands are negative. In this case, they are negated.
The sum output by the binary adder is corrected as needed with the assistance of the output stage. This is required when no carry has appeared in the BCD addition. In this case, the number 6 must be subtracted from the result of the binary adder.
A circuit arrangement constructed in such fashion

REFERENCES:
patent: 3339064 (1967-08-01), Koizumi et al.
patent: 3935438 (1976-01-01), Grupe
patent: 3958112 (1976-05-01), Miller
patent: 4441159 (1984-04-01), Hart
IC'S Make Parallel Arithmetic Practical, by P. Kintner, Control Engineering, Oct. 1972, pp. 48-49.

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