Circuit arrangement for a data acquisition circuit of a PCM proc

Details Circuit arrangement for a data acquisition circuit of a PCM proc Circuit arrangement for a data acquisition circuit of a PCM proc

1984-05-18

1987-01-13

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375 34, 375101, 328164, 358155, 360 45, H04B 112

Patent

active

046370366

ABSTRACT:
A circuit arrangement comprises a frequency response control circuit for controlling the level around a particular frequency of an input PCM signal in accordance with a control signal which is produced as a function of the difference between levels of positive peaks and/or negative peak corresponding to a logic bit pattern 1010 of a data synchronous signal of the PCM signal having a predetermined format. The level detection may be performed by a plurality of sample-and-hold circuits, and the difference is obtained by way of an adder-subtractor. The circuit may be arranged to constitute either a feedback loop in which level detection is effected by using a frequency response controlled PCM signal, or a feedforward system in which level detection is effected by using the input PCM signal whose frequency response has not been controlled. An output signal from the frequency response control circuit is then applied to two comparators of a conventional data acquisition circuit.

REFERENCES:
patent: 3660821 (1972-05-01), Weber et al.
patent: 3832577 (1974-08-01), Harr
patent: 3840892 (1974-10-01), Hayashi
patent: 4241455 (1980-12-01), Eibner
patent: 4245345 (1981-01-01), Gitlin et al.
patent: 4358790 (1982-11-01), Summers
Carlson, Communications Systems, McGraw-Hill, 1975, Second Edition, p. 23.
IBM TDB, vol. 22, No. 8A, Jan. 1980, pp. 3328-3330.

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