Static information storage and retrieval – Interconnection arrangements – Transistors or diodes
Reexamination Certificate
2011-08-09
2011-08-09
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
Transistors or diodes
C365S063000, C365S226000, C365S189060, C365S096000
Reexamination Certificate
active
07995367
ABSTRACT:
The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.
REFERENCES:
patent: 4730129 (1988-03-01), Kunitoki et al.
patent: 4995004 (1991-02-01), Lee
patent: 5334880 (1994-08-01), Abadeer et al.
patent: 5404049 (1995-04-01), Canada et al.
patent: 5418487 (1995-05-01), Armstrong, II
patent: 5731733 (1998-03-01), Denham
patent: 5976943 (1999-11-01), Manley et al.
patent: 6091273 (2000-07-01), Bernstein et al.
patent: 6384664 (2002-05-01), Hellums et al.
patent: 6421293 (2002-07-01), Candelier et al.
patent: 6487134 (2002-11-01), Thoma et al.
patent: 6525955 (2003-02-01), Smith et al.
patent: 6775186 (2004-08-01), Eshel
patent: 6819144 (2004-11-01), Li et al.
patent: 2002/0008544 (2002-01-01), Lim et al.
patent: 2002/0057604 (2002-05-01), Khouri et al.
patent: 2004/0052106 (2004-03-01), Ohtani
patent: 2004/0105301 (2004-06-01), Toyoda et al.
patent: 2005/0212086 (2005-09-01), Unterleitner
patent: 1 195 771 (2002-04-01), None
J. Fellner et al., “Lifetime Study for a Poly Fuse in a 0.35μM Polycide CMOS Process”, 2005 IEEE International Reliability Physics Symposium Proceedings 43rdAnnual, San Jose, California, Apr. 17-21, 2005, IEEE Catalog No. 05CH37616, ISBN: 0-7803-8803-8, Library of Congress No. 82-640313, pp. 446-449.
J. Fenner et al., “One Time Programming Cell Using More than Two Resistance Levels of a PolyFuse”, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference 27thannual, San Jose, California, Sep. 18-21, 2005, IEEE Catalog No. 05CH37658, ISBN: 0-7803-9023-7, Library of Congress Catalog No. 85-653738, pp. 263-266.
Bösmüller Peter
Fellner Johannes
Schatzberger Gregor
austriamicrosystems AG
Cohen Pontani Lieberman & Pavane LLP
Ho Hoai V
Norman James G
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