Circuit arrangement and method for reducing an alignment...

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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C341S172000

Reexamination Certificate

active

06927718

ABSTRACT:
The invention proposes includes a circuit that operates continuously in the time domain on the basis of the sigma-delta principle. The circuit includes at least one integrating circuit that is characterized by a first transfer function, and has a comparison circuit having a clock signal applied thereto that compares an output signal coming from the at least one integrating circuit with a reference signal and delivers a binary output signal. The circuit further includes an apparatus for signal feedback that is connected to the output of the comparison circuit and to the input of the at least one integrating circuit, and is characterized by a second transfer function. Further, an alignment device is provided that aligns the second transfer function of the apparatus for signal feedback with the first transfer function of the integrating circuit.

REFERENCES:
patent: 5894284 (1999-04-01), Garrity et al.
patent: 6323796 (2001-11-01), Krone et al.
patent: 6452531 (2002-09-01), Miller et al.
patent: 6489914 (2002-12-01), Jones et al.
patent: 6628216 (2003-09-01), Chen et al.
patent: 6744392 (2004-06-01), Melanson
patent: 6809672 (2004-10-01), Gupta
patent: 2002/0011945 (2002-01-01), Locher
“A Tri-Mode Continuous-Time ΣΔ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver”, Robert Van Veldhoven, IEEE International Solid-State Circuits Conference, 2003, pp. 60-61, date unknown.
“High-Speed ΣΔ Modulators With Reduced Timing Jitter Sensitivity”, Susan Luschas and Hae-Seung Lee, IEEE Transactions on Circuits and Systems-II; Analog and Digital Signal Processing, vol. 49, No. 11, Nov., 2002, pp. 712-719.

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