Circuit arrangement and data processing method

Details Circuit arrangement and data processing method Circuit arrangement and data processing method

2006-09-05

2006-09-05

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S118000, C702S182000, C702S183000

Reexamination Certificate

active

07103494

ABSTRACT:
A circuit arrangement in which two parallel subcircuits having a same functionality have a same input signal applied to them, and their output signals are compared in a common comparison arrangement. The two subcircuits are designed differently in terms of sensitivity to changes in environmental or operating parameters. Impermissible environmental parameters are indicated if the output signals differ from one another, and an alarm is generated.

REFERENCES:
patent: 5307299 (1994-04-01), Stein et al.
patent: 5798756 (1998-08-01), Yoshida et al.
patent: 6246970 (2001-06-01), Silverbrook
patent: 6867623 (2005-03-01), Nishizono
patent: 6927580 (2005-08-01), Wuidart et al.
patent: 2002/0130248 (2002-09-01), Bretschneider et al.
patent: 2004/0205095 (2004-10-01), Gressel et al.
patent: 196 26 184 (1998-01-01), None
patent: 0 874 369 (1998-10-01), None
patent: 1 154 375 (2001-11-01), None
Khoo et al., Single-Transistor Transparent-Latch Clocking, 1995, IEEE Integrated Circuits and Systems Laboratory, University of California, Los Angeles, pp. 331-341.

Affiliated with

Also associated with

Rating

Circuit arrangement and data processing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement and data processing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement and data processing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3543302