Circuit arrangement

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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377 47, 327175, H03K 506

Patent

active

053651197

ABSTRACT:
A signal generator includes a frequency divider having an input node for receiving a first signal having a first frequency f.sub.1 and a single output node for outputting a second signal having a second frequency f.sub.2, wherein a ratio f.sub.1 /f.sub.2 is equal to an odd number that is equal to or greater than three. A synchronous delay circuit has an input node coupled to the single output node of the frequency divider and an output node for outputting a third signal that is delayed in time with respect to the second signal by an amount that is a function of a period of the first signal. Logic is provided having a first input node coupled to the single output node of the frequency divider and a second input node coupled to the output node of the delay circuit. The logic has an output node for outputting a fourth signal having the second frequency f.sub.2 and a 50% duty cycle. In a further embodiment the signal generator outputs a frequency that is (2n+1)/2 of the input frequency, where n any positive integer.

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Electronic Engineering, Jun. 1979, p. 35, Applied Ideas, "Three-phase clock from reference clock using TTL", Afzal, Mohammed.
EDN, 13 Oct. 1988, p. 254, Design Ideas.

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