Circuit arrangement

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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Details

C361S820000, C257S723000, C257S724000

Reexamination Certificate

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06927969

ABSTRACT:
First and second chips each having a transistor are provided. The first chips are arranged along a first axis on a first metallic body in side-by-side and interspaced manner. The second chips are arranged parallel to the first axis on a second metallic body in a side-by-side and interspaced manner. The second chips are arranged perpendicular to the first axis opposite an area of the first body and are each connected to the opposite area via at least one bonding connection. The first chips, with regard to the third axis, are arranged opposite an area of the second body, which is located between adjacent second chips. A third metallic body is arranged on the second body and comprises projections each of which being arranged on one of the areas of the second body. The first chips are each connected to the opposite projection via at least one bonding connection.

REFERENCES:
patent: 3971062 (1976-07-01), Merkle
patent: 4241360 (1980-12-01), Hambor et al.
patent: 5994768 (1999-11-01), Fogelson
patent: 6021048 (2000-02-01), Smith
patent: 6031278 (2000-02-01), Onoda et al.
patent: 6049975 (2000-04-01), Clayton
patent: 6121681 (2000-09-01), Tanaka et al.
patent: 6707673 (2004-03-01), Duesman et al.
patent: 6737741 (2004-05-01), Imasu et al.

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