Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-01-22
2004-04-06
Cuneo, Kammie (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090, C324S073100, C324S076520
Reexamination Certificate
active
06717427
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a circuit arrangement for controlling a first terminal and a second terminal of a preferably contactless integrated circuit, particularly for testing a CMOS circuit.
BACKGROUND OF THE INVENTION
In a multitude of integrated circuits that are used nowadays, the transmission of data from and to the integrated circuit as well as the transfer of energy to the integrated circuit is effected in a contactless way, for example, by means of microwaves, lightwaves, capacitive coupling or inductive coupling. In the latter case, the integrated circuit can be controlled via at least a coil which is connected to the integrated circuit via a first terminal and a second terminal.
In this context, particularly after manufacturing the integrated circuit which may be arranged on the wafer of the carrier substrate of semiconducting or insulating material, it is necessary to control this integrated circuit by way of contacts via the first and second terminal, i.e. to control them separately via the coil interfaces, for example, for the purpose of subjecting the integrated circuit to a trial and test operation. To this end, the integrated circuit is powered with an AC voltage via the coil interfaces and a bidirectional exchange of data takes place simultaneously.
When an integrated circuit is to be tested in the conventional way, a test arrangement with two tester outputs and one modulation output is customarily provided. The two tester outputs generate carrier clocks of opposite phase which are connected to the first and second terminal of the integrated circuit via resistors internally preceding the relevant tester outputs. If the voltage at the modulation output is higher than the voltage at the tester outputs, diodes arranged between the tester outputs and the modulation output are blocked and the carrier amplitude is equal to the voltage at the two tester outputs. By decreasing the voltage at the modulation output, the two tester outputs are loaded and the carrier amplitude is decreased. The modulation index can be adjusted via the voltage at the modulation output.
For a simultaneous multi-test, the modulation in this conventional test arrangement is to be separately built up for every individual integrated circuit. In other words, this means that three channels—corresponding to the two tester outputs and the modulation output—of the conventional test arrangement are required for modulating the integrated circuit. Since a further test-pin channel is additionally required for each integrated circuit, a test arrangement with, for example, 64 channels can subject a maximum number of sixteen integrated circuits to a parallel test.
A circuit arrangement for ASK demodulation (ASK=amplitude shift keying) is known from EP 0 949 786 A1. This document describes a circuit arrangement for demodulating a voltage which is (ASK)-modulated by changing the amplitudes between the low and the high level, particularly for a chip card which comprises a bandpass filter for suppressing interference having a low frequency with respect to the modulation frequency, for suppressing the carrier frequency and for generating a pulse upon a change of the amplitudes between the low level and the high level, as well as a threshold value switch with which the demodulated voltage is generated by impressing it with the pulses and by switching it between two states.
The conventional circuit arrangements described above have in common that compensating currents occur at the tester outputs so that the circuit arrangements become elaborate and complicated. Moreover, the conventional circuit arrangements described above are suitable for a simultaneous multi-test to a limited extent only because a relatively high number of channels of the circuit arrangement is required for each integrated circuit.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a circuit arrangement of the type described in the opening paragraph in which a multitude of integrated circuits can be tested simultaneously while using a low-cost structure. Moreover, the present invention is to provide a circuit arrangement for a simple write/read unit assigned to the integrated circuit.
This object is achieved by the characteristic features defined in claim 1. Advantageous embodiments and further improvements of the present invention are defined in the dependent claims.
In accordance with the teaching of the present invention, the circuit arrangement comprises at least a control stage, at least a first driver stage and at least a second driver stage which is complementary to the first driver stage. The first driver stage and the second driver stage operate to a certain extent as a bridge stage which provides a symmetrical supply via the first terminal and the second terminal of the integrated circuit, in which the first driver stage is connected to the first terminal of the integrated circuit and the second driver stage is connected to the second terminal of the integrated circuit—or conversely.
The amplitude modulation is effected via the switching of the respective power supply voltage between the two driver stages, in which the power supply voltages of the two driver stages are switched at different instants in accordance with the teaching of the present invention. To this end, the two driver stages are impressed with symmetrical clock signals which are inverted with respect to each other so that two equally long clock phases [a] and [b] are produced at the output of the driver stages. In clock phase [a] the power supply voltage is connected to the output of the relevant driver stage and in clock phase [b] the reference potential is connected to the output of the relevant driver stage.
The switching of the power supply voltage between the two driver stages mentioned above is effected in accordance with the teaching of the present invention in clock phase [b] in which the power supply voltage is not connected to the output of the relevant driver stage. Since the two driver stages operate with a mutually inverted clock, the relevant instant of switching is different for the two driver stages.
In connection with the present invention, those skilled in the art will appreciate that the circuit arrangement, although having a relatively simple structure, is implemented for data transmission by means of ASK modulation (ASK=amplitude shift keying), for example, for testing an integrated circuit or for a write/read unit assigned to an integrated circuit.
In contrast to the prior-art circuit arrangement disclosed in EP 0 949 786 A1, a variable degree of modulation with adjustable pulse rates and with adjustable pulse widths provides the possibility of response of all reception/transmission parameters of the integrated circuit, also by means of a standard test arrangement. Particularly when using such a standard test arrangement, a reduction of the test period by about 50% as compared with conventional circuit arrangements is possible with the circuit arrangement according to the invention, which circuit arrangement functions in this case as a bridge circuit or a bridge stage.
The invention also relates to a preferably contactless integrated circuit, particularly a CMOS circuit controlled and particularly tested by at least a circuit arrangement of the type described hereinbefore.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5235273 (1993-08-01), Akar et al.
patent: 6282682 (2001-08-01), Walker et al.
patent: 6469514 (2002-10-01), Okayasu
patent: 2003/0001557 (2003-01-01), Pisipaty
patent: 2003/0016041 (2003-01-01), Ueda et al.
patent: 0949786 (1998-11-01), None
Jp11355367; A (Sony Corp), Dec. 24, 1999.
Liebig Michael
Thiel Holger
Tobergte Wolfgang
Cuneo Kammie
Patel Paresh
Simons Kevin
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