Circuit arrangement

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Logarithmic

Reexamination Certificate

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Details

C327S350000

Reexamination Certificate

active

06559705

ABSTRACT:

The invention relates to a circuit arrangement for generating and amplifying a DC signal, referred to as level voltage, whose value is essentially proportional to the logarithm of the voltage amplitude of the input signal, the circuit arrangement comprising an amplifier circuit having at least two amplifier stages. In general, the present invention relates to the field of analog integrated circuits.
Such circuit arrangements fulfill two functions. They are used for amplifying an AC voltage signal which is applied to the circuit arrangement via its input terminals; simultaneously, such a circuit arrangement limits the amplitude of the output signal. Consequently, the term “limiter amplifier” is also used for such a circuit arrangement. Such limiter amplifiers are used in, for example, the frequency-modulated IF amplification in radio receivers or when gaining carriers from amplitude-modulated signals.
When a simple extension, for example, in the form of a rectifier stage is realized in such a limiter amplifier, a direct voltage can be generated which within wide ranges is proportional to the logarithm of the amplitude of the voltage of the input signal. When the amplitude of the output signal is plotted against the logarithm of the amplitude of the input voltage, a wide range of the input voltage shows a straight part with an essentially constant increase. This straight part is generally indicated as the “level characteristic”. In this case, the start, i.e. the variation of this level characteristic at small input voltages is dependent on the selected amplification of the limiter amplifier. In other words, this means that the variation of the level characteristic at small input voltages cannot be chosen independently of the gain factor of the circuit arrangement.
The prior art discloses a possibility to extend the level characteristic to larger input voltages (cf. document WO 97/14212), but this does not answer the question in how far level indications can be extended to smaller input voltages. A conventional possibility of extending the level characteristic to smaller input voltages is the addition of a further amplifier stage. However, this requires a larger amplification so that it may give rise to difficulties regarding negative feedback and/or an offset and/or a larger current consumption and/or the oscillation stability.
Based on the above-mentioned drawbacks and shortcomings, the present invention has for its object to provide a circuit arrangement of the type described in the opening paragraph, in which the level characteristic can be extended towards small input signals without increasing the amplification, for example, by means of adding a further amplifier stage.
This object is solved by a circuit arrangement as defined in claim
1
. Advantageous embodiments and essential further improvements of the present invention are defined in the dependent claims.
Regarding the present invention, it should be noted that the emitter follower (collector circuits) of the full-wave rectifier of the last amplifier stage have a significant share in the level characteristic when the voltage at the respective base is of the order of the temperature voltage.
For this reason, the at least one differential amplifier stage, in combination with the at least one multiplier stage, contributes to the level characteristic below the range of a temperature voltage, which contribution is the larger as the input voltage at the circuit arrangement is smaller (principally, a linearly amplifying DC amplifier whose output voltage is proportional to the difference between the two input voltages is concerned in this respect. The basic circuit comprises two transistors combined at the emitter and fed from a common constant current source. The differential amplifier is usually symmetrical because temperature influences and non-linearities are then substantially compensated, with a small offset behavior as a result).
In accordance with the teaching of the present invention, the at least one differential amplifier stage is arranged parallel to the emitter followers of the last amplifier stage, and its output signals are multiplied in at least one multiplier stage. This product is added in the at least one current adder unit to the parts of the level characteristic of the other amplifier stages preceding the last amplifier stage and in this way supplies a significant contribution to the level characteristic already at input signals below the rectifying action of the emitter followers (collector circuits) of the last amplifier stage.
In accordance with a particularly inventive further improvement of the circuit arrangement, the slope of the additional part of the characteristic can be varied towards smaller level voltages of the circuit arrangement via the current supplied by at least a current source of the differential amplifier. The level characteristic can also be extended at very small currents in the added differential amplifier stage when high-ohmic resistors are inserted.
As regards the present invention, those skilled in the art will appreciate that an extension of the level indication or an extension of the level characteristic towards smaller voltages can be achieved with the circuit arrangement—at a smaller current consumption—, without an offset problem and/or negative feedback problem occurring—as in conventional circuit arrangements with additional amplifier stages.
The invention also relates to an integrated circuit, particularly an analog integrated circuit, including at least a circuit arrangement of the type described hereinbefore.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.


REFERENCES:
patent: 5298811 (1994-03-01), Gilbert
patent: 5417166 (1995-05-01), Credle, Sr.
patent: 5506537 (1996-04-01), Kimura
patent: 6483367 (2002-11-01), Kohsiek
patent: WO0233822 (2001-10-01), None

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