Circuit, architecture and method for reducing power consumption

Details Circuit, architecture and method for reducing power consumption Circuit, architecture and method for reducing power consumption

1999-11-03

2000-12-26

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365236, G11C 800

Patent

active

061669911

ABSTRACT:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.

REFERENCES:
patent: 5247164 (1993-09-01), Takahashi
patent: 5247655 (1993-09-01), Khan et al.
patent: 5254888 (1993-10-01), Lee et al.
patent: 5337285 (1994-08-01), Ware et al.
patent: 5430393 (1995-07-01), Shankar et al.
patent: 5452434 (1995-09-01), MacDonald
patent: 5563839 (1996-10-01), Herdt et al.
patent: 5625311 (1997-04-01), Nakatsu
patent: 5789952 (1998-08-01), Yap et al.
patent: 5848014 (1998-12-01), Yukshing
patent: 6088290 (2000-07-01), Ohtake et al.

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