Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-12-22
2002-03-26
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000, C365S189050
Reexamination Certificate
active
06363031
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to synchronous integrated circuits generally and, more particularly, to a circuit, architecture and method for reducing power consumption in a synchronous integrated circuit.
BACKGROUND OF THE INVENTION
Present day electrical products often incorporate semiconductor devices. The use of semiconductor devices has enabled electrical products to accomplish tasks more quickly and efficiently than was previously possible. Improvements in the semiconductor devices have included reducing the amount of power consumed by the devices. One way that semiconductor devices can reduce power consumption is a “powered down” or “sleep” mode. In the sleep mode, input buffers and other current sinking elements are disabled. The electronic device enters the “powered down” or “sleep” mode after receiving a power reduction command signal.
An example of a conventional power reduction command signal is the Jedec-standard “ZZ” signal. A Jedec-standard package for semiconductor devices such as synchronous integrated circuits defines a “ZZ” input pin. The “ZZ” pin is configured to place the device in a “sleep” mode for reducing power consumption. A synchronous integrated circuit (e.g., an SRAM) is clocked with an externally applied clock signal. The “ZZ” sleep command signal can be activated asynchronously relative to the external clock.
According to conventional approaches, before activating the “ZZ” sleep mode, a synchronous integrated circuit is preferably first deselected by controlling chip enable input signals (e.g., CE and/or CEb). Therefore, to effectively use the reduced power “sleep” mode, (i) a relatively complex setup procedure must be followed, (ii) circuitry must be provided for generating the “ZZ” command signal, and a “ZZ” pin must be provided to receive the “ZZ” command signal.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
The objects, features, and advantages of the present invention include providing a circuit, architecture and method for reducing power consumption in a synchronous integrated circuit that may (i) be implemented without the need for a separate sleep pin (ii) eliminate the need for circuitry to generate a sleep signal, and/or (iii) automatically power down a chip that is deselected or unused after a predetermined length of time.
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Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Hoang Huan
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