Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-09-09
2004-08-24
Tran, Khai (Department: 2631)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
06782064
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit, architecture and method for asynchronous switching between two clock domains, particularly between two asynchronous clock domains generally and, more particularly, to a circuit, architecture and method for asynchronous clock domain switching.
BACKGROUND OF THE INVENTION
Data synchronized between two asynchronous clock domains need access to a common resource. Asynchronous switching between asynchronous clocks can lead to truncated or short clock pulses and/or metastability problems.
Referring to
FIG. 1
, a conventional circuit
10
for asynchronous switching between two clock domains is shown. The circuit
10
comprises a multiplexer
12
, a multiplexer
14
, and a shared resource
16
. A first data signal DATA
1
and a second data signal DATA
2
are received by the multiplexer
12
. A first clock signal CLOCK
1
and a second clock signal CLOCK
2
, which are not synchronized to each other, are received by the multiplexer
14
. A control signal CONTROL is received by the multiplexer
12
at an input
18
and the multiplexer
14
at an input
20
. The multiplexer
12
presents a data signal DATA to the shared resource
16
. The multiplexer
12
presents the signal DATA in response to the signal DATA
1
, the signal DATA
2
and the signal CONTROL. The multiplexer
14
presents a clock signal CLOCK to the shared resource
16
. The multiplexer
14
presents the signal CLOCK in response to the signal CLOCK
1
, the signal CLOCK
2
and the signal CONTROL.
The disadvantage of circuit
10
is incomplete clock pulses can be generated at indeterminate times. Such incomplete clock pulses result in metastability problems, particularly when the control signal is not synchronized to either or both of the clock signals CLOCK
1
and CLOCK
2
and/or the data signals DATA
1
and DATA
2
.
In general, most designers shy away from switching clock circuits, such as the circuit
10
. The designers would duplicate the multiplexers
12
and
14
as well as the shared resource
16
in FIG.
1
and switch back and forth on the side of the (no longer shared) resource
16
where the clock domains are the same. Thus, the clocks are synchronously switched in a single clock domain, rather than asynchronously switched across two clock domains.
A summary of asynchronous clock switching schemes is shown in FIGS.
2
(A)-
2
(C). FIG.
2
(A) shows a simplified diagram of the multiplexer
14
of FIG.
1
. FIG.
2
(B) shows a clock-switching circuit
20
. The clock switching circuit
20
comprises a buffer
22
and a buffer
24
. The buffer
22
receives a control signal CONTROL at an input
26
. The buffer
24
receives the signal CONTROL at an input
28
. The signal CONTROL tri-states one of the two buffers
22
or
24
to produce a selected clock signal SWITCHED CLOCK.
FIG.
2
(C) shows an alternative clock switching circuit
30
. The circuit
30
comprises a multiplexer
32
and a synchronizer
34
. A control signal CONTROL is received by the synchronizer
34
. The synchronizer
34
synchronizes to one of the two clock signals CLOCK
1
or CLOCK
2
. In this case, the other clock signal CLOCK
1
or CLOCK
2
may, when initially selected, lead to the metastability problems described above.
SUMMARY OF THE INVENTION
The present invention concerns, in one aspect, a switch for at least two clock domains, comprising (a) first and second synchronizers in a first clock domain, (b) third and fourth synchronizers in a second clock domain, and (c) a state machine configured to interface with and/or receive signals from the synchronizers, thereby controlling switching between the first and second clock domains.
The present invention concerns, in a further aspect, a method of switching between first and second clock domains, comprising (a) driving a switch output at a logic level controlled by a first clock domain in response to a first control signal state, (b) driving the switch output at a first predetermined logic level for a predetermined period of time in response to (i) a second control signal state and (ii) either (A) a predetermined transition of both the first clock domain and a second clock domain, or (B) both the first and second clock domains having the first predetermined logic level and (c)enabling only the second clock domain to drive the switch output.
The objects, features and advantages of the present invention include providing one or more of the following new features and/or functions (a) asynchronous switching between two asynchronous clocks and (b) the switch architecture and circuitry composed of four synchronizers and an asynchronous state machine.
REFERENCES:
patent: 5675615 (1997-10-01), Watt
patent: 5811995 (1998-09-01), Roy et al.
Burd Kevin M
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Tran Khai
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