Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2002-02-28
2004-10-26
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S055000
Reexamination Certificate
active
06809569
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a cross-coupled load circuit.
BACKGROUND OF THE RELATED ART
A cross-coupled load circuit is often used in many applications.
FIG. 1
illustrates a circuit
100
that is often referred to as a cross-coupled load circuit. Ideally, current I
1
equals current I
3
and current I
2
equals current I
4
during operation. Or in other words, I
1
+I
2
=I
3
+I
4
. However, this matching relationship between currents is generally not precisely observed. Current mismatch may occur due to transistor channel length modulation effect. Also, for certain voltages DCCP and DCCN applies to nodes
101
and
102
, respectively; transistors in circuit
100
may not be in respective saturation regions. If a transistor is not in a saturation region, current cannot be precisely controlled. If the current cannot be controlled, the cross-coupled load will not be balanced. A n-type transistor is operating in a saturation region when the transistor's gate voltage V
G
minus the transistor's drain voltage V
D
is less than the transistor's threshold voltage V
T
. A transistor's threshold voltage V
T
is defined as the voltage between a transistor's gate V
G
and a transistor's source V
S
at which a transistor begins to conduct.
Circuit
100
includes transistors that should operate in respective saturation regions. Transistors
107
,
108
,
109
and
110
are coupled to ground
111
and act as switches, respectively, for power consumption purpose when respective portions of circuit
100
are not in use, responsive to a NOP signal at node
120
. Transistors
103
and
106
are likely to be in a saturation region as they are diode connected. Yet, transistors
104
and
105
may not be in a saturation region for certain voltage values of DCCP and DCCN. For transistors
104
and
105
to be in a saturation region, |DCCP−DCCN|<V
T
. As transistors continue to scale down along with corresponding threshold voltages V
T
, it will be more difficult to ensure that transistors
104
and
105
are in saturation regions for voltage values of DCCP and DCCN.
While it may be desirable to provide a relatively small voltage drop |DCCP−DCCN| to ensure that transistors
104
and
105
are in a saturation region and thus current matching is occurring, a relatively larger voltage drop |DCCP−DCCN| may be desirable for other reasons. Even if a particular transistor operating condition, also known as a Process Voltage Temperature (“PVT”), allows for a transistor to have a relatively small V
T
, other PVT corners may allow an unacceptably small voltage drop |DCCP−DCCN| for a particular application. For example,
FIG. 2
illustrates a transistor in a Fast Fast Hot (“FFH”) operating condition represented by curve
210
having the lowest V
T
with a voltage drop |DCCP−DCCN| 205, or approximately 180 mv. As can be seen, a voltage drop |DCCP−DCCN| reduces to 204, or approximately 105 mv, for a Typical Typical (“TT”) operating condition represented by curve
211
and further reduces to a voltage drop |DCCP−DCCN| 203, or approximately 60 mv, for a Slow Slow Hot (“SSH”) operating condition represented by curve
212
. Accordingly, if a circuit application requires a voltage drop |DCCP−DCCN| of greater than 60 mv, a transistor having this lowest threshold voltage V
T
cannot be used. Thus, some applications that require a larger voltage drop over DCCP and DCCN are not able to use transistors with relatively low threshold voltages V
T
.
Moreover, circuit
100
may be used for correcting a duty cycle of a clock signal in a receiving or transmitting circuit. Thus, any current mismatch may lead to an erroneous duty cycle of a clock signal and thereby increase data error rates.
Therefore, it is desirable to provide a circuit and method for providing a cross-coupled load circuit with current mirrors that allows the transistors to operate in a saturation region in response to a relatively large voltage drop over DCCP and DCCN. It is also desirable to provide an apparatus that produces an improved clock signal and thereby reduces data error rates of incoming serial data.
SUMMARY
A circuit, apparatus and method for providing a cross-coupled load with built-in current mirrors are provided in embodiments of the present invention.
In an embodiment of the present invention, a circuit comprises a first node for providing a variable first voltage and a second node for providing a variable second voltage, wherein the first voltage is different from the second voltage. A first transistor is coupled to the first node and provides a first current responsive to a first control voltage being applied to the first transistor gate. A second transistor is coupled to the second node and provides a second current responsive to a second control voltage being applied to the second gate. A first control circuit is coupled to the first transistor gate and the second node. The first control circuit provides the first control voltage responsive to the variable second voltage. A second control circuit is coupled to the second gate and the first node. The second control circuit provides the second control voltage responsive to the variable first voltage.
According to an embodiment of the present invention, the first and second transistors operate in a saturation region.
According to another embodiment of the present invention, the circuit further comprises a third transistor that is coupled to the first node and provides a third current responsive to the first variable voltage. A fourth transistor is coupled to the second node and provides a fourth current responsive to the second variable voltage.
According to another embodiment of the present invention, the first current approximately equals the fourth current and the third current approximately equals the second current.
According to another embodiment of the present invention, the first variable voltage and the second variable voltage represent a clock signal.
According to an embodiment of the present invention, the clock signal has an amplitude of greater than approximately 400 mv.
According to an embodiment of the present invention, the first current, the second current, the third current and the fourth current are used to provide a duty cycle correction signal.
According to an embodiment of the present invention, the first transistor, the second transistor, the third transistor and the fourth transistor are n-type transistors.
According to an embodiment of the present invention, the first control circuit comprises a fifth transistor that is coupled to a voltage source. A sixth transistor is coupled to the fifth transistor. The fifth transistor gate is coupled to the first transistor gate. The sixth transistor is coupled to the voltage source. A seventh transistor is coupled to the sixth transistor. The seventh transistor gate is coupled to the second node.
According to another embodiment of the present invention, the second control circuit comprises an eighth transistor that is coupled to the voltage source. A ninth transistor is coupled to the eighth transistor and the ninth transistor gate is coupled to the first node. A tenth transistor is coupled to the voltage source. An eleventh transistor is coupled to the tenth transistor. The eleventh transistor gate is coupled to the second transistor gate.
According to an embodiment of the present invention, the circuit is a cross-coupled load with built-in current mirrors circuit used in a double data rate receiving circuit for improving a clock signal.
According to an embodiment of the present invention, the circuit is a cross-coupled load with built-in current mirrors circuit used in a double data rate transmitting circuit for improving a clock signal.
According to an embodiment of the present invention, the circuit is in a memory device.
According to an embodiment of the present invention, the circuit is i
Tran Chanh
Wang Yueyong
Nguyen Minh
Rambus Inc.
Vierra Magen Marcus Harmon & DeNiro LLP
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