Amplifiers – With semiconductor amplifying device – Including balanced to unbalanced circuits and vice versa
Reexamination Certificate
2002-06-27
2004-10-12
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including balanced to unbalanced circuits and vice versa
C330S253000
Reexamination Certificate
active
06803823
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a receiving circuit, and in particular a single-ended signal to differential signal conversion circuit.
BACKGROUND OF THE RELATED ART
A differential amplifier often provides a differential output voltage in response to two input voltages.
FIG. 1
illustrates a circuit
100
that is often referred to as a differential amplifier. A voltage source V
DD
is applied to sources of transistors
101
and
103
. Gates of transistors
101
and
103
are coupled to ground
109
. Drains of transistors
101
and
103
are coupled to terminals
121
and
122
, respectively. Terminals
121
and
122
output a differential output voltage V
OUT
. Drains of transistors
101
and
103
are also coupled to drains of transistors
102
and
104
, respectively. An input voltage V
IN
is applied to a gate of transistor
102
and a reference voltage V
REF
is applied to the gate of transistor
104
. Sources of transistors
102
and
104
are coupled to a current source, and in particular transistor
108
having a source coupled to ground
109
and a drain coupled to the sources of transistors
102
and
104
. A bias voltage V
BIAS
is applied to a gate of transistor
108
. Transistors
101
and
102
form a first electrical path from a voltage source V
DD
and current source (transistor)
108
while transistors
103
and
104
form a second electrical path. An advantage of such a differential amplifier is that the matched electrical paths cancel undesirable voltage swings common to input voltages, which may for instance be caused by temperature variations or noise, whereas differences between the input voltages are amplified.
A differential output voltage V
OUT
, illustrated by curve
203
in
FIG. 2
c
, is output at terminals
121
and
122
in response to voltage V
IN
illustrated by curve
200
in
FIG. 2
a
. In particular, curve
202
, illustrated in
FIG. 2
b
, represents an output voltage at terminal
121
and curve
201
represents an output voltage at terminal
122
in response to V
IN
represented by curve
200
illustrated in
FIG. 2
a
. Reference voltage V
REF
is represented by curve (flat line)
204
in
FIG. 2
a
. The two output voltages at terminals
121
and
122
are combined to obtain the differential output voltage V
OUT
as illustrated by curve
203
in
FIG. 2
c
. Differential output voltage V
OUT
has a duty cycle of approximately 53.6%, as opposed to an ideal 50%.
A receiving circuit often includes amplifying stage and sampling stage. Differential amplifiers are often used in amplifying stage of a receiving circuit in order to restore/amplify the incoming data. Ideally, the amplifier should maintain the timing information of the incoming data in order to have the sampling stage operate correctly, i.e., if a periodic incoming data has 50% duty cycle, the amplified differential signal should also have 50% duty cycle.
However, certain serial data signals are single-ended signals. This single-ended signal usually needs to be converted into a differential signal, and a differential amplifier is commonly used for this purpose. However, a differential amplifier may create erroneous or unbalanced amplified differential signals and degrade timing margin of a receiving circuit. For example, when a double date rate transmitter is transmitting a single-ended signal of “1” and “0” during a clock cycle, an optimal signal sampling stage will receive an amplified signal with an evenly distributed bit duration of “1” and “0”. This will typically ensure both “1” and “0” have optimal timing margin. If any one of these two bits “1” or “0” have a longer bit duration than the other, system timing margin is degraded. A data input signal may include either a relatively large and/or small voltage level swing. A differential amplifier may be designed to handle a relatively low voltage level swing. This means a differential amplifier is acting as a gain stage. Yet a gain stage generally does not handle input signals properly with large voltage level swings, as one of the input transistors will be pushed out of saturation. For relatively large single-ended input voltage signals as illustrated in
FIG. 2
a
, where one of the input devices is pushed into linear region, current steering does not work properly. Thus, the characteristic of the amplified differential signals may be different for large voltage swings in large data eyes than for small voltage swings in small data eyes. Furthermore, the input voltage swings of a receiving circuit may not be predictable. Thus, an amplifier that can properly operate with both large and small voltage swing is desirable.
Some differential amplifiers have addressed unbalanced amplified differential signals by providing unbalanced loads on respective electrical paths. This technique may reduce duty cycle error for large input voltage levels, but it degrades performance for small voltage inputs. Further, such a technique does not offer common mode noise rejection, since each electrical path should be ideally symmetrical in nature.
Therefore, it is desirable to provide a circuit and method for providing a balanced differential output voltage signal for both relatively small and large voltage level inputs while also being able to reject noise. It is also desirable to provide an apparatus that produces an improved duty cycle clock signal and thereby reduce data error rates of incoming serial single-ended data.
SUMMARY
A circuit, apparatus and method for providing a balanced differential signal from incoming single-ended serial data having high or low voltage swings are provided in embodiments of the present invention.
In an embodiment of the present invention, a circuit comprises a voltage source and a current source coupled to a node. A first electrical path is coupled to the voltage source and the node. A second electrical path is coupled to the voltage source and the node. The first path includes a first transistor having a first gate and a first channel. The first gate is adapted to receive a reference voltage. The second path includes a second transistor having a second gate and a second channel. The second gate is adapted to receive a data voltage that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path, and provides a predetermined resistance responsive to a node voltage at the node.
According to another embodiment of the present invention, the circuit further comprises a signal processing circuit that is coupled to the variable resistor and the node. The signal processing circuit generates a control signal responsive to the node voltage.
According to an embodiment of the present invention, the circuit comprises a third transistor having a third gate and a third channel. The first path includes the third channel having a first resistance between the voltage source and the first transistor. The second path includes a fourth transistor having a fourth gate and a fourth channel having a second resistance between the voltage source and the second transistor.
According to another embodiment of the present invention, the current source includes a fifth transistor having a drain coupled to the node and a source coupled to a ground. The fifth transistor has a gate adapted to receive a bias voltage.
According to still another embodiment of the present invention, the variable resistor includes a sixth transistor having a source, a drain and a gate. The source is coupled to the first path and the drain is coupled to the second path.
According to an embodiment of the present invention, the signal processing circuit comprises a seventh transistor having a source, a drain and a gate. The source is coupled to the voltage source and the gate is coupled to the sixth transistor gate. An eighth transistor has a source, a drain and a gate. The eighth transistor drain is coupled to the seventh transistor drain and the eighth transistor gate is coupled to the node.
According to an embodiment of the present inventi
Tran Chanh
Wang Yueyong
Nguyen Khanh Van
Rambus Inc.
Vierra Magen Marcus Harmon & DeNiro LLP
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