Circuit and test method for testing input cells

Details Circuit and test method for testing input cells Circuit and test method for testing input cells

1997-02-18

1998-04-14

Nguyen, Hoa T.

Excavating

371 222, 371 2231, G01R 3128

Patent

active

057401802

ABSTRACT:
A circuit (100) comprises a built-in test circuit (150) which verifies the proper operation of input cells (130) when they receive signals at a first level (71) and at a second level (72). The test circuit (160) comprises a first and a second logic (110, 120) which receive power only when a test is performed. Thereby power consumption of the test circuit (160) is reduced. The first and the second logic (110, 120) are conveniently formed by a combination of parallel coupled transistors acting in an logical OR-function.

REFERENCES:
patent: 4875003 (1989-10-01), Burke
patent: 4912709 (1990-03-01), Teske et al.
patent: 5132937 (1992-07-01), Tuda et al.
patent: 5345423 (1994-09-01), Koh et al.
patent: 5351213 (1994-09-01), Nakashima

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