Circuit and method to facilitate threshold voltage...

Details Circuit and method to facilitate threshold voltage... Circuit and method to facilitate threshold voltage...

2001-10-15

2004-10-19

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S356000, C307S110000, C323S313000

Reexamination Certificate

active

06806762

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to operation of transistors and integrated circuits and, more particularly, to a system and method to facilitate extracting a threshold voltage of a MOSFET, which further can be employed to operate an associated circuit, such as capacitor multiplier.
BACKGROUND OF THE INVENTION
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are often used to implement a variety of analog functions and digital logic, such as in the form of large scale integrated circuits (LSI) and very large scale integrated circuits (VLSI). A MOSFET can be controlled to provide various outputs as a function of its operating parameters. One important operating parameter is the threshold voltage V
T
. The V
T
corresponds to a gate voltage that causes the onset of strong inversion in the channel of the MOSFET, allowing significant current flow through the device.
FIG. 1
illustrates a graphical representation of drain current I
D
plotted versus gate-source voltage V
GS
, such as when the MOSFET operates in its linear region. The current-voltage characteristics can be divided into different regions, including a cut-off region
2
, a weak inversion region
2
, and a strong inversion region
6
. Thus, a different level of inversion is provided for different gate-source voltages V
GS
. A similar estimation-by-linear-extrapolation method can also be used for a MOSFET in the saturation region. Usually, this test is performed with the gate tied to the drain to ensure saturation, with the threshold voltage V
T
being extrapolated from a curve of {square root over (I
D
)} plotted versus V
GS
.
Several approaches have been developed to determine the onset of strong inversion and, in turn, the V
T
. One common approach is a constant current method in which the V
T
can be obtained with a single voltage measurement. The efficacy of this method generally depends on the selected current, as different drain currents tend to result in different threshold voltages. Another approach, often used by researchers, is a linear extrapolation method. In this method, a maximum transconductance is employed to locate a point of maximum slope along a plot of drain current versus gate-source voltage. However, the transconductance is dependent on the series resistance of the MOSFET, which can introduce errors.
Several other approaches have been developed to extract the threshold voltage and mitigate the dependency on the series resistance associated with the linear extrapolation method. One such approach is referred to as the second derivative method. In this method, the V
T
is calculated from the peak of the second derivative of drain current over gate-source voltage. This approach is sensitive to noise in the measurements as well as requires substantial processing to locate the peak of the second derivative. Other approaches to derive an indication of V
T
include a ratio method and a quasi-constant-current method, which have various limitations in addition to their complexities.
FIG. 2
illustrates an example of a capacitor multiplier circuit, which includes MOSFET devices MN
1
and MN
2
as an AC current mirror. The current mirror and capacitor C
1
constitute an AC feedback loop, which tends to increase the effective capacitance seen at the output node by a factor of one plus N, where N is the ratio of aspect ratios (W/L) of MN
1
to MN
2
. The effective increase in capacitance is due to a reduction in the current available to charge C
1
. When current I
O
in
FIG. 2
charges the node V
O
during a transient condition, the current of the capacitor C
1
is mirrored from MN
2
to MN
1
, and amplified in the process by a factor of N. The gained current is pulled out of the output node V
O
, reducing the current available to charge the capacitor C
1
. The feedback loop reduces the charging current, which has the substantially the same effect on the charge-up time as increasing the size of the capacitor.
For the feedback loop to function correctly, the voltage at the NMOS gates should be greater than or equal to the MOSFET threshold voltage, which permits the MOSFETs to conduct. Thus, with the capacitor multiplier circuit of
FIG. 2
, all of I
0
's current flows into the capacitor until the gate node of the current mirror reaches a voltage equal to V
T
. The result is the initial transient behavior, such as shown in FIG.
3
. In
FIG. 3
, the output voltage V
O
is plotted (in volts) versus time (in seconds), indicated at
10
. The graph
10
illustrates the dV/dt characteristics of the capacitor multiplier of FIG.
2
. The output voltage quickly ramps from 0V to V
T
, at which point the current mirror begins to operate. The slew rate then decreases to the value determined by the feedback loop of C
1
. Theoretically, a capacitor multiplier should provide substantially linear dV/dt characteristics
10
without the initial charge-up to V
T
, more closely resembling the charging of an ideal capacitor, also shown in
FIG. 3
at
12
.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the present invention provides a system for extracting the threshold voltage of a MOSFET. A first stage includes an input operative to receive a first input current. A gate node is electrically coupled to the first input. A second stage includes a gate node and an input operative to receive a second input current. A voltage divider or other network can be coupled between the input of the second stage and the gate node of the first stage, such that an intermediate node of the network is coupled to the gate node of the second stage. With proper biasing conditions and MOSFET sizing, the output voltage of the circuit is approximately equal to the threshold voltage for the MOSFET. In accordance with a particular aspect of the present invention, the output voltage from the voltage extraction system can be provided to a capacitor multiplier to mitigate startup offset usually associated with operation of the active capacitor multiplier, thereby improving the operation of the capacitor multiplier.
Another aspect of the present invention provides a substantially accurate capacitor multiplier system. The capacitor multiplier includes first and second stages coupled together at a common gate node. The first stage includes a first input that receives an input current and an ac feedback network, such as a capacitor, is coupled between an output of the second stage and the first input. A threshold voltage extraction system provides an output having a value functionally related to a threshold voltage for a MOSFET device associated with the second stage of the capacitor multiplier. The output from the threshold voltage extraction system is provided to a second input of the capacitor multiplier, such that the threshold voltage is provided to an common gate node of the capacitor multiplier so as to mitigate a startup offset of the capacitor multiplier circuit when the bias current is applied to the first input.
The following description and the annexed drawings set forth in certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 3911296 (1975-10-01), Davis
patent: 5095223 (1992-03-01), Thomas
patent: 5672960 (1997-09-01), Manaresi et al.
patent: 5952874 (1999-09-01), Manaresi et al.
patent: 6084475 (2000-07-01), Rincon-Mora
X. Zhou, et al.;

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