Circuit and method to externally adjust internal circuit timing

Details Circuit and method to externally adjust internal circuit timing Circuit and method to externally adjust internal circuit timing

1997-09-04

1999-05-11

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365201, G11C8/00

Patent

active

059035129

ABSTRACT:
A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

REFERENCES:
patent: Re35065 (1995-10-01), Ohsawa
patent: 5406522 (1995-04-01), Hirano
patent: 5517462 (1996-05-01), Iwamoto et al.
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5745430 (1998-04-01), Wong et al.
patent: 5751655 (1998-05-01), Yamazaki et al.

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