Circuit and method to balance delays through true and...

Details Circuit and method to balance delays through true and... Circuit and method to balance delays through true and...

2006-03-07

2008-10-28

Tan, Vibol (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S141000, C327S065000, C327S258000, C326S082000, C326S026000

Reexamination Certificate

active

07443217

ABSTRACT:
A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

REFERENCES:
patent: 5949269 (1999-09-01), Allen
patent: 6208184 (2001-03-01), Demicheli et al.
patent: 6529033 (2003-03-01), Park et al.
patent: 6700420 (2004-03-01), Spehar
patent: 2002/0121918 (2002-09-01), Alani et al.
patent: 2004/0066216 (2004-04-01), Spehar
patent: 2004/0202270 (2004-10-01), Lentine et al.
patent: 2005/0146367 (2005-07-01), Chauhan et al.

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