Circuit and method to adjust memory timing

Details Circuit and method to adjust memory timing Circuit and method to adjust memory timing

1997-03-28

1999-03-23

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365205, G11C 810

Patent

active

058869450

ABSTRACT:
The circuit includes a memory element connected to an enabling input receiving an enabling signal, and in turn including a first reset circuit receiving an internal reset signal, and a second reset circuit receiving an external timing control signal, to generate an operating step enabling signal having a first switching edge on receiving the enabling signal, a second switching edge on receiving the reset signal, and a third switching edge on receiving the external timing control signal. A control input receives a timing mode signal, and is connected to the first and second reset circuits to enable them selectively. By enabling the second reset circuit and supplying the external timing control signal, in successive cycles, with different delays in relation to the enabling signal, different readings of the memory are enabled to characterize the response and optimize the timing of the memory device.

REFERENCES:
patent: 4425633 (1984-01-01), Swain
patent: 4575812 (1986-03-01), Fitzpatrick
patent: 4687951 (1987-08-01), McElroy
patent: 5303188 (1994-04-01), Kohno
patent: 5452311 (1995-09-01), Wells et al.
patent: 5608687 (1997-03-01), Komared et al.

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