Circuit and method of timing data transfers

Details Circuit and method of timing data transfers Circuit and method of timing data transfers

1994-08-31

1996-10-08

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 327279, H03M 900

Patent

active

055635946

ABSTRACT:
A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written. Once the proper delay is determined by experimentation, the phase delay logic controls the phase of the transfer data control signal to request more data at the correct time, or present more data at the correct time, to allow maximum operating speed for the data converter.

REFERENCES:
patent: 4218758 (1980-08-01), Allen et al.
patent: 4445215 (1984-04-01), Svendsen
patent: 4815107 (1989-03-01), Kishimoto et al.
patent: 5379038 (1995-01-01), Matsumoto

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