Circuit and method of resetting a master/slave flipflop

Details Circuit and method of resetting a master/slave flipflop Circuit and method of resetting a master/slave flipflop

1992-02-03

1992-10-13

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 3072722, 3072723, 307289, H03K 3286, H03K 3289

Patent

active

051553830

ABSTRACT:
A master/slave flipflop uses a reset circuit to initialize its output to a known state. A data input signal and a reference signal are received at first and second inputs of a differential transistor input stage respectively for developing first and second output signals having opposite logic states at first and second nodes. A locking circuit locks the logic states of the first and second output signals at the first and second nodes respectively. A reset circuit reduces the second output signal at the second node upon receiving a reset signal to establish a logic low state at the second node and a logic high state at the first node which transfer through the slave portion as the output signals of the flipflop circuit.

REFERENCES:
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patent: 5001361 (1991-03-01), Tamamura et al.
patent: 5027005 (1991-06-01), Kitsuta et al.
patent: 5099142 (1992-03-01), Barre

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