Circuit and method of reducing phase jitter in a phase lock loop

Details Circuit and method of reducing phase jitter in a phase lock loop Circuit and method of reducing phase jitter in a phase lock loop

1991-09-09

1992-06-30

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 18, 331 25, H03L 718

Patent

active

051266938

ABSTRACT:
A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.

REFERENCES:
patent: 4651026 (1987-03-01), Serfaty et al.

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