Circuit and method of reading cells of an analog memory array, i

Details Circuit and method of reading cells of an analog memory array, i Circuit and method of reading cells of an analog memory array, i

1998-07-22

1999-10-26

Phan, Trong

Static information storage and retrieval

Floating gate

Multiple values

36518519, 3651852, 36518521, 36518533, G11C 1604, G11C 1606

Patent

active

059739592

ABSTRACT:
A reading circuit comprises a current mirror circuit connected, at a first and a second output node, to the drain terminals of an array cell and of a reference cell; a comparator whose inputs are connected to the output nodes of the current mirror circuit; a ramp generator having an enabling input connected to the output of the comparator and an output connected to the control terminal of the reference cell. Biasing the gate terminal of the array cell to a constant voltage, when the currents flowing in the array cell and in the reference cell are equal, the value assumed by the ramp voltage is proportional to the threshold value of the array cell; at that time the comparator is triggered and discontinues the ramp increase, supplying as output the desired threshold value.

REFERENCES:
patent: 5091888 (1992-02-01), Akaogi
patent: 5335198 (1994-08-01), Buskirk et al.
patent: 5351212 (1994-09-01), Hashimoto
patent: 5699295 (1997-12-01), Yero
patent: 5712815 (1998-01-01), Bill et al.
patent: 5805500 (1998-09-01), Campardo et al.
patent: 5838612 (1998-11-01), Calligaro et al.

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