Circuit and method of maximum voltage bias control

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S306000, C326S080000, C326S068000

Reexamination Certificate

active

06377106

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to voltage selection circuits, and more particularly, to voltage selection circuits which select the maximum voltage of two input voltage supply potentials and provide the maximum voltage at the output with additional current drive.
BACKGROUND OF THE INVENTION
Complimentary MOS (CMOS) processing is used for semiconductors which employ both N-type and P-type devices. The N-type and P-type devices coexist on the same substrate through the use of well regions. The well regions act as isolation boundaries between the N-type and P-type devices and are typically electrically shorted to either the source or drain regions. CMOS devices are used, for example, for up/down, DC-DC voltage regulator controller applications. Both N-type and P-type MOS Field Effect Transistors, NMOS and PMOS, respectively, are used to control current flow from the voltage source, typically a battery. The NMOS device, for example, is typically used to conduct current from the voltage supply or battery to charge the inductor during up-conversion mode. The PMOS device, for example, is then used to conduct current from the inductor during the discharge cycle of the inductor. Since the MOS devices are used in an up/down voltage converter, two sources of supply voltage exists within the converter. In an up-conversion mode, the input voltage is at a lower potential than the output voltage. In a down conversion mode, the output voltage is at a lower potential than the input voltage. In either case, a maximum supply potential exists, input voltage or output voltage, which should be used to control the switching devices during regulation.
Prior art up/down, DC-DC converters which employ the PMOS and NMOS switch topology, typically employ a fixed logic supply potential to supply the top rail supply voltage to the control logic. Using a fixed logic supply potential, however, causes additional switching losses, since the fixed supply voltage must be larger than either the input or output voltages and larger than required gate voltages are used. A need exists, therefore, for a maximum voltage bias control device, which is capable of determining the maximum of two supply potentials and delivering the maximum potential, with additional current drivers, as the supply voltage to be used by the switch control circuitry.


REFERENCES:
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5457420 (1995-10-01), Asada
patent: 6043699 (2000-03-01), Shimizu
patent: 6057718 (2000-05-01), Keeth
patent: 6323704 (2001-11-01), Pelly et al.

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