Circuit and method of latching a bit line in a non-volatile memo

Static information storage and retrieval – Floating gate

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36518511, 36518905, 36523008, G11C 1614

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active

059782625

ABSTRACT:
A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38, 44) each having outputs respectively coupled to bit lines (50, 54, 56), and control inputs coupled to a common control line (132). The bit lines each include a latch (60, 62, 64) that is set to provide a programming voltage (VPP) during write mode. The bit lines have serial switches (78, 80, 82) that break continuity when writing to the latches. The bit line latches are made transparent to the bit lines during read mode. The common control line is coupled through a programming transistor (130) to an erase line (72). The erase line must be driven to a programming voltage during erase mode. The erase line uses one of the bit line latches to provide its programming voltage.

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patent: 4408306 (1983-10-01), Kuo
patent: 4751678 (1988-06-01), Raghunathan
patent: 5297081 (1994-03-01), Challa
patent: 5297096 (1994-03-01), Terada et al.
patent: 5337281 (1994-08-01), Kobayashi et al.
patent: 5526307 (1996-06-01), Yiu et al.
patent: 5533123 (1996-07-01), Force et al.

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