Circuit and method of JTAG testing multichip modules

Details Circuit and method of JTAG testing multichip modules Circuit and method of JTAG testing multichip modules

1994-06-06

1996-10-22

Nguyen, Hoa T.

Excavating

371 223, 371 225, H04B 1700

Patent

active

055684920

ABSTRACT:
A multichip module (10) having one or more IC die (12-18) supports JTAG testing with a plurality of registers (20-26) within each IC die. JTAG testing requires a one cycle delay bypass mode where registers within an IC not under test are bypassed. To support bypass mode when JTAG testing the multichip module on a printed circuit board, a bypass circuit around the multichip module provides the one cycle delay. The bypass circuit monitors the test data signals to the multichip module and enters bypass mode upon detecting a predetermined sequence of logic states during the instruction sequence. Otherwise, the test data signal passes through a plurality of registers within each IC die. The detection may be performed by counting logic states or otherwise monitoring in the instruction sequence.

REFERENCES:
patent: 5230000 (1993-07-01), Mozingo et al.
patent: 5281864 (1994-07-01), Hahn et al.
patent: 5319646 (1994-07-01), Simpson et al.

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