Circuit and method of indicating data hold-time

Details Circuit and method of indicating data hold-time Circuit and method of indicating data hold-time

1994-07-18

1996-08-20

DeBoer, Todd

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 371 62, 324617, H03M 900

Patent

active

055482856

ABSTRACT:
A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.

REFERENCES:
patent: 5291141 (1994-03-01), Farwell et al.

Affiliated with

Also associated with

Rating

Circuit and method of indicating data hold-time does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method of indicating data hold-time, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method of indicating data hold-time will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2333122