Circuit and method for wrap-around sign extension for signed num

Details Circuit and method for wrap-around sign extension for signed num Circuit and method for wrap-around sign extension for signed num

1998-06-19

2000-06-06

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708628, G06F 752

Patent

active

060731567

ABSTRACT:
A multiplier is configured to multiply two signed values to generate sum and carry bit groups representing, in redundant form, a product of the first and second signed values. A sign determining circuit is configured generate a sign bit representing a sign of the product. An extension unit is configured to receive the sum most significant bit, the sign bit, and the carry most significant bit. The extension output terminal configured to carry a replacement bit and an extension bit, the replacement bit having a same weight as the sum most significant bit. The extension unit is structured such that the replacement bit has one binary state only if the sum most significant bit and the carry most significant bit are different. The extension unit is structured such that the extension bit has one binary state only if the sign bit is a binary zero and the sum most significant bit and the carry most significant bit are the same.

REFERENCES:
patent: 4926371 (1990-05-01), Vassiliadis et al.
patent: 5251167 (1993-10-01), Simmonds et al.
patent: 5943250 (1999-08-01), Kim et al.
patent: 5954791 (1999-09-01), Green et al.

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