Circuit and method for wrap-around sign extension for signed num

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

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Details

708628, G06F 752

Patent

active

060818239

ABSTRACT:
A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

REFERENCES:
patent: 4926371 (1990-05-01), Vassiliadis et al.
patent: 5251167 (1993-10-01), Simmonds et al.
patent: 5943250 (1999-08-01), Kim et al.
patent: 5954791 (1999-09-01), Green et al.

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