Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By frequency
Reexamination Certificate
2000-06-30
2001-12-18
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By frequency
C327S049000
Reexamination Certificate
active
06331792
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an improved circuit and method for frequency acquisition and, more particularly, to a frequency detector circuit and method for unlimited range frequency acquisition.
BACKGROUND OF THE INVENTION
Generally, all communication systems include a transmitter, a receiver and a communication channel. A fiber optic communication system is a lightwave system employing optical fibers as the communication medium. Optical fibers transport the optical signal (lightwave) with relatively little power loss. Power or fiber loss is largely due in part to noise or jitter in the signal. Signal noise can be caused by many different sources, such as, for example, thermal noise, shot noise and imperfect fiber.
Power loss consideration is an important design parameter. In particular, the power loss determines the spacing of repeaters in a long-haul lightwave system. During normal signal transmission it is necessary to periodically regenerate the optical signal with a repeater. Repeater stations include an optical receiver-transmitter pair that detects the incoming optical signal, recovers the electrical bit stream, and converts it back to an optical bit stream by modulating the transmitter. The optical receiver portion typically consists of a digital optical receiver. The digital optical receiver includes a clock and data recovery (CDR) component comprising a decision circuit and a clock recovery circuit. First the decision circuit compares the output from the channel to a threshold level at a sampling time determined by the clock-recovery circuit. Next, the decision circuit decides whether the signal corresponds to bit “1” or bit “0.”
The purpose of the clock-recovery circuit is to isolate a spectral component at a frequency (f) equal to the bit rate (B) from the received signal. This component provides information about the bit slot to the decision circuit and helps to synchronize the decision process. In the case of RZ (return-to-zero) format, a spectral component at f=B is present in the received signal and a narrow bandpass filter such as a surface-acoustic-wave (SAW) filter can isolate this component easily. Clock recovery is more difficult in the case of NRZ (non-return-to-zero) format because the received signal lacks a spectral component at f=B. NRZ is the standard data format in SONET (synchronous optical network) systems and SONET is the standard for the telecommunications industry.
The CDR circuit restores and retimes the NRZ bit sequence by extracting the clock signal from the received data. Because the spectrum of a NRZ random bit sequence does not have a spectral component at the bit rate f=B, the component has to be created using nonlinear signal processing. The component at f=B is generated, filtered and phase aligned to the NRZ data to yield a clock signal. In general, a phase and frequency locked loop (PFLL) is used to perform both the filtering and the phase alignment. The incoming data is resampled with a clean clock to filter, for example, jitter present on the data.
The clean clock is provided by a voltage controlled oscillator (VCO). Typically, the frequency and phase of the NRZ data controls the input voltage to the VCO in a loop configuration. The VCO frequency is adjusted in response to the input NRZ data frequency and phase. Ideally, the VCO free running frequency (i.e., without control from the loop) should be as close as possible to the frequency of the incoming data. However, in an integrated CDR, the VCO free running frequency can vary considerably from the data frequency, e.g., up to ±50% difference. In fact, the data frequency may be outside the maximum frequency tuning range of the VCO or outside the maximum range of a conventional frequency detector. In both cases, the limited range of the frequency detector prevents the CDR circuit from adjusting the VCO frequency to the data frequency.
The CDR generally has two loops, a phase loop to clean up and lock the phase, and a frequency loop to adjust the VCO frequency closer to the incoming data frequency. Referring now to
FIG. 1
, an exemplary schematic of a two loop CDR is shown. As illustrated, CDR
100
comprises a phase loop
102
, a frequency loop
104
, a VCO
106
and a frequency window
112
.
VCO
106
is a standard voltage-controlled oscillator commonly known in the industry including, but not limited to, a ring oscillator or an LC oscillator. One of skill in the art will have familiarity with the design of VCO
106
; many such products are readily available on the market.
Frequency window
112
is a counter that monitors the frequencies of loop
104
comparing the frequencies of the beat between the incoming NRZ data and the VCO. Once the frequencies approach an acceptable range, frequency window
112
sends a signal to shut off loop
104
, causing a switch coupled to the input of VCO
106
to engage phase loop
102
.
Phase loop
102
includes a phase detector
108
. Generally, phase detector
108
has a very narrow frequency range and therefore, the VCO frequency must be close to the incoming data frequency for the phase loop to lock.
Because frequency loop
104
has a wider frequency acquisition range than phase loop
102
, the frequency loop typically receives the incoming NRZ data when the CDR system is initialized. Frequency loop
104
includes a frequency detector
110
. In general, a conventional frequency detector of the prior art has an acquisition range around ±30% if working with no external reference.
A common frequency detector used industry-wide is the Pottbäcker frequency detector. For a complete understanding of the Pottbäcker FD, refer to: A. Pottbäcker, U. Langmann, and H. -U. Schreiber, “An 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s, “
IEEE J. Solid-State Circuits
, vol. 27, no. 12, pp. 1747-1751, Dec. 1992, the disclosure of which is incorporated herein by reference. The incoming data frequency is compared to the VCO frequency by the Pottbäcker frequency detector. If the incoming data frequency is higher or lower than the VCO frequency, the frequency detector will output an averaged signal to adjust the VCO frequency closer to the data frequency. The change of the VCO frequency continues until the frequency of the VCO nears the incoming data frequency (e.g., typically around ±1% difference).
The frequency acquisition range of a conventional frequency detector
110
is wider than the range of phase detector
108
, however the range is still limited. The VCO free running frequency must lie within approximately ±30% of the output of a conventional frequency detector for loop
104
to effectively change the VCO frequency. In operation, however, the difference between the VCO frequency and the bit rate (B) can be as high as ±50%.
Referring now to
FIG. 2
, an exemplary averaged output signal (e.g. after low pass filter (LPF
2
) of
FIG. 1
) of a conventional (e.g., Pottbäcker) frequency detector is shown. For exemplary purposes only, the frequency is varying from zero to twice the incoming data frequency. As we know, NRZ format lacks a spectral component at f=B. As shown in
FIG. 2
, a change of sign in average occurs at 2000 MHz(e.g., 2.0 GHz) representing the spectral component at f=B. Thus, 2000 MHz is the center frequency or the desired lock point in the exemplary output signal of FIG.
2
. Under ideal conditions, the VCO frequency will be the centered frequency and lock at the zero average point.
If the VCO free running frequency is 3000 MHz (below the 0 average), the averaged output of the conventional frequency detector will be set negative and the VCO frequency will be driven lower towards 2000 as expected. On the other hand, if the free running frequency is 1500 (above the 0 average), the averaged output will be set positive and the VCO frequency will be driven higher towards 2000, again as expected. But, if the free running frequency is 1000 the output is set negative and the VCO frequency will be drive
Conexant Systems Inc.
Cox Cassandra
Donohue Michael J.
Seed IP Law Group PLLC
Tran Toan
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