Circuit and method for trimming locking of integrated circuits

Details Circuit and method for trimming locking of integrated circuits Circuit and method for trimming locking of integrated circuits

2005-04-19

2005-04-19

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

C327S526000, C365S225700

Reexamination Certificate

active

06882214

ABSTRACT:
A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.

REFERENCES:
patent: 4412241 (1983-10-01), Nelson
patent: 5079516 (1992-01-01), Russell et al.
patent: 6338032 (2002-01-01), Chen
patent: 6410398 (2002-06-01), Forel et al.
patent: 6472897 (2002-10-01), Shyr et al.
S. Laville, S. Pontarollo, “Integrated Offset Trimming Technique”, ST Microelectronics DSG, and D. Dufaza, D. Auvergne, LIRMM (date unknown).

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