Circuit and method for trimming integrated circuits

Details Circuit and method for trimming integrated circuits Circuit and method for trimming integrated circuits

2008-01-15

2008-01-15

Kerveros, James C. (Department: 2117)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting input voltage to output current or vice versa

C324S765010

Reexamination Certificate

active

07319346

ABSTRACT:
A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

REFERENCES:
patent: 3890610 (1975-06-01), Cahen
patent: 4150366 (1979-04-01), Price
patent: 4225878 (1980-09-01), Dobkin
patent: 4335371 (1982-06-01), Connolly, Jr. et al.
patent: 4412241 (1983-10-01), Nelson
patent: 4665356 (1987-05-01), Pease
patent: 4713602 (1987-12-01), Ueda
patent: 4823320 (1989-04-01), Smayling et al.
patent: 5079516 (1992-01-01), Russell et al.
patent: 5353028 (1994-10-01), de Wit et al.
patent: 5361001 (1994-11-01), Stolfa
patent: 5426616 (1995-06-01), Kajigaya et al.
patent: 5563549 (1996-10-01), Shieh
patent: 5568083 (1996-10-01), Uchiyama et al.
patent: 5663589 (1997-09-01), Saitoh et al.
patent: 5675280 (1997-10-01), Nomura et al.
patent: 5682049 (1997-10-01), Nguyen
patent: 5757264 (1998-05-01), Petit
patent: 5768290 (1998-06-01), Akamatsu
patent: 5771012 (1998-06-01), Shu et al.
patent: 5838076 (1998-11-01), Zarrabian et al.
patent: 6184720 (2001-02-01), Kim et al.
patent: 6472897 (2002-10-01), Shyr et al.
First Office Action from European Patent Office dated Mar. 26, 2004.
Second Office Action from European Patent Office dated Sep. 2, 2004.

Affiliated with

Also associated with

Rating

Circuit and method for trimming integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for trimming integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for trimming integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2761034