Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
1998-12-23
2002-09-17
Luu, Matthew (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S428000, C345S581000, C345S583000, C345S586000, C345S589000
Reexamination Certificate
active
06452603
ABSTRACT:
BACKGROUND OF THE INVENTION
U.S. Pat. No. 5,751,292 granted to Emmot describes a texture for use in displaying surface detail of an object modeled in a computer (column 1, lines 12-15). The computer uses a number of texels (column 7, line 54) that are point elements of a two-dimensional image (referred to as a “texture”, e.g. surface detail of leather) and that are mapped onto a surface of a three-dimensional object (column 1, lines 44-53), e.g. a seat (thereby to form the image of a leather seat). Each texel in a texture is normally defined by S and T coordinates (sometimes called “U and V coordinates”) of the texel. The S and T coordinates identify the location of the center of a texel relative to the two-dimensional texture (column 1, lines 59-60). For example, texel 12 in
FIG. 1A
has the coordinates S
12
and T
12
.
To eliminate aliasing, texels can be “filtered” (low pass) to obtain a value at the location of a to-be-displayed pixel by use of adjacent texels to generate the filtered texel. For example, Emmot states that “for each display screen pixel that is rendered with texture data from a two-dimensional texture map, as many as four texels . . . or eight texels . . . may be accessed from the cache memory to determine the resultant texture data for the pixel” (column 14, lines 22-27).
The above-described filtering of texels can be of three types. As stated by Emmot, “[w]hen a point sampling interpolation mode is established, the resultant texel data equals the single texel that is closest to the location defined by the pixel's S, T coordinates in the texture map. Alternatively, when bilinear or trilinear interpolation is employed, the resultant texel data is respectively a weighted average of the four or eight closest texels . . . The weight given to each of the multiple texels is determined based upon the value of the gradient and [fractional] components of the S and T coordinates provided to the texel interpolator . . . ” (column 14, lines 32-41).
Specifically, the intensity I for a point
9
(
FIG. 1A
) is obtained by bilinear interpolation of four texels
10
-
13
(also called a “quadruplet” and abbreviated as “quad”) that are adjacent to each other. If the four texels
10
-
13
have intensities I
0
-I
3
, intensity I is given by I=Ct((Cs(I
1
−I
0
)+I
0
)−(Cs(I
3
−I
2
)+I
2
))+(Cs(I
3
−
12
)+I
2
), where Cs and Ct are the distances of point
9
from the (S,T) coordinates of texel
12
. See U.S. Pat. No. 5,706,481 (incorporated by reference herein in its entirety) at column 8, lines 50-59. In bilinear filtering, the four texels
10
-
13
are from a texture at a single magnification (called “level of detail” and abbreviated as “LOD”).
Trilinear filtering uses a first filtered texel obtained by bilinear interpolation of a first quad at a level of detail L (having an integer value, e.g. 2), and a second filtered texel obtained by bilinear interpolation of a second quad at a level of detail L+1 as follows. An interpolation is performed between the first and second filtered texels to obtain a filtered texel at a third LOD (having a real value, e.g. value 2.5) that is between L and L+1. Therefore, trilinear filtering normally requires that a cache address generator
6
(
FIG. 1B
; see U.S. Pat. No. 5,327,509) generate the addresses of four texels at level of detail L and four texels at level of detail L+1. Cache address generator
6
supplies the eight addresses to a texture pattern memory
7
(
FIG. 1B
) that hold texels belonging to each of L and L+1 levels of detail. A texture trilinear interpolator
8
uses the eight texels to perform the interpolation.
SUMMARY
A circuit and process in accordance with the invention perform trilinear filtering using a number (e.g. 4) of texels (called “nearest texels”) that are nearest to a to-be-displayed pixel, and also use an additional number (e.g. 12) of texels (called “surrounding texels”) that surround the nearest texels. The nearest texels and the surrounding texels are all from only one level of detail L, while a filtered texel generated by the circuit and process is at a level of detail between L and L+1. The filtered texel is used in rendering the to-be-displayed pixel, and can be made identical to a texel obtained by trilinear filtering in the prior art.
In a first embodiment, the circuit and process use the nearest texels and the surrounding texels (all of which are at a level of detail L) to generate a first quad of texels at a coarse level of detail L+1. Thereafter, the generated quad (at the coarse level of detail L+1) is used with a second quad of the nearest texels (at the level of detail L) to perform trilinear filtering. In the first embodiment, generation of the first quad is performed by a coarse texel generator, and interpolation between two levels of detail L and L+1 is performed by an interpolation circuit that are both included in the circuit (also called “single level trilinear circuit”) of the first embodiment.
Specifically, the coarse texel generator has input terminals (hereinafter “fine texel terminals”) coupled to two buses: the nearest texel bus and to the surrounding texel bus to receive therefrom a total of sixteen texels at the level of detail L. The coarse texel generator also has an output bus (hereinafter “coarse texel bus”) to carry away the quad of coarse texels generated therein. The nearest texels (received from the nearest texel bus) and the surrounding texels (received from the surrounding texel bus) form four quads, wherein all four quads are adjacent to each other and are from the level of detail L, and each quad touches at least two other quads (in a manner similar to the four quadrants of a square). The coarse texel generator includes arithmetic units that average texels in the four quads (individually for each quad) to form four coarse texels that are supplied to the coarse texel bus.
The interpolation circuit has several groups of input terminals. A first group of input terminals (hereinafter “coarse quad terminals”) are coupled to the coarse texel bus to receive the quad of coarse texels. A second group of input terminals (hereinafter “fine quad terminals”) are coupled to the nearest texel bus to receive a quad of nearest texels. A third group of input terminals (hereinafter “coordinate terminals”) are coupled to the coordinate input bus to receive therefrom fractional parts of the S and T coordinates (also called “S and T coordinate fractions”) for the filtered texel. A fourth group of input terminals (hereinafter “LOD terminals”) are coupled to the level of detail bus. The interpolation circuit also has output terminals (hereinafter “filtered texel output terminals”) that are coupled to the texel output bus to supply thereto the filtered texel obtained by interpolation. Specifically, the interpolation circuit performs trilinear interpolation between the four coarse texels from the coarse texel generator and four of the fine texels (one fine texel from each of the four quads) by use of the texel's S and T coordinate fractions and the level of detail fraction to generate the filtered texel on the texel output bus.
In the first embodiment, the circuit and process generate texels at a coarse level of detail L+1 twice: a first time to create all texels at the coarse level of detail L+1 (for an initial set of mipmaps), and a second time to create a quad of coarse texels that are used for trilinear interpolation. Therefore, when generating the coarse texels for a second time, all texels at the coarse level of detail L+1 are not created. Instead, in this embodiment, only the specific quad of coarse texels that are required at the moment for trilinear interpolation are created.
The regeneration of coarse texels (i.e. generation of the coarse texels a second time) is performed in the coarse texel generator that is included in a texture system of a graphics processor, and the resulting coarse texels are used directly (without storage in main memory) by the i
Chung Daniel J
Luu Matthew
NVIDIA US Investment Company
Townsend and Townsend / and Crew LLP
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