Patent
1997-02-28
1998-08-18
Heckler, Thomas M.
G06F 112
Patent
active
057969957
ABSTRACT:
A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at different multiples of a system clock signal. The clock generation circuitry (20) includes a counter (60) that indicates, for a given frequency ratio, signals (REGION) indicating the current phase region of the faster clock (PCLK) relative to the slower clock (BCLK). The clock domain translation circuit (50a) includes a series of input registers (82, 84) in sequence, with the output of each as well as the input signal line (IN PCLK) coupled to inputs of a multiplexer (80). The multiplexer (80) selects either the input signal directly or the output of one of the registers for application to an output register (90), clocked by the slower clock signal (BCLK), depending upon the phase region of the faster clock (PCLK) relative to the slower clock (BCLK) for communication of that signal. As a result, the input digital signal is held for enough time to be properly clocked in, depending upon the phase region, thus enabling frequency ratios of non-integer values to be utilized in system operation.
REFERENCES:
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5692166 (1997-11-01), Milhizer et al.
Bosshart Patrick W.
Nasserbakht Mitra
Chastain Lee E.
Donaldson Richard L.
Heckler Thomas M.
Kesterson James C.
Texas Instruments Incorporated
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