Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-15
2003-06-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S210130
Reexamination Certificate
active
06574146
ABSTRACT:
TECHNICAL FIELD
This invention relates to a circuit and a method for timing multi-level non-volatile memories.
In particular, the invention relates to a read timing circuit for regulating the step of reading from a multi-level non-volatile memory, which circuit is adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path, which dummy path includes at least one dummy wordline being applied a supply voltage and associated with a dummy decoding circuit portion arranged to receive an ATD signal.
BACKGROUND OF THE INVENTION
As is well known, in a two-level non-volatile memory which employs a floating-gate NMOS transistor as an elementary cell, a capability to modulate the threshold voltage of the memory cell is utilized for discriminating between two logic states. A first logic state (logic “1”) corresponds to a situation of no charge being contained in the floating gate, as would be typical of a virgin or an erased cell. The other logic state (logic “0”) corresponds to the floating gate having a sufficient number of electrons stored therein to produce a substantial rise of its threshold, signifying a programmed state of the cell.
To read from the memory cell, the gate is applied a read voltage Vread, and the current flowing through the cell is sensed: if the cell is written, its threshold voltage is higher than Vread and, therefore, no current will be passed. On the other hand, if the cell has been erased, its threshold voltage must be adequate to let current flow through it. The threshold voltage spread of the cells, following an electric erasement, is in the range of about 1V to 2.5V. Ensuring that there are no depleted cells and avoiding damage to the thin oxide of the transistor which comprises the cell, during the reading operation, are the governing factors for the lower limit, the upper limit being instead dictated by the intrinsic extent of the spread. The programmed spread would generally lie above 5V.
But in the instance of multi-level non-volatile memories, this spread is entirely different. In these memory types, the charge stored on the floating gate is further split into a number of spreads equal to 2
n
, where “n” is the number of bits to be stored in the same cell. Thus, with two bits per cell, there would be four spreads.
Comparative threshold voltage spreads, for a two-level memory and a multi-level memory having two bits per cell, are illustrated schematically by the plots in
FIGS. 1A and 1B
. As can be seen, the multi-level structure involves a reduction in the gap between voltage values, and an increased read voltage.
Also known is that memory cells are organized as rows and columns of a matrix, and that the physical organization of the memory matrix is decided by two fundamental considerations:
space occupation to be the least possible, for obvious reasons of cost; and
memory access time, that is the time taken by the device to present the contents of the addressed location on its outputs, to fill ever stricter user's specifications. (Some 100 ns, nowadays.)
With access time being fundamental in determining the quality of a memory, this parameter is foremost in the designer's choices, above all of the matrix row size.
Schematized in
FIG. 2
is the structure of a non-volatile memory of the NOR type. The gate terminals of the cells are interconnected at the rows or wordlines of the matrix, and the drain terminals are connected together to provide the columns or bitlines of the matrix.
Row and column binary decoders are respectively associated with the rows and the columns of the matrix, and enable each cell to be located univocally by addresses provided from outside the memory. The source terminals of the cells are connected to a common “source line,” which is the same as a voltage reference, e.g., a ground reference, in the instance of EPROMs.
In Flash EEPROMs which allow for the memory matrix to be erased electrically, the source line is instead driven by purposely arranged circuitry.
The drain terminals are usually connected to form the bitlines by a metallization line. The gate terminals of one row are interconnected by a strip of a conductive material such as polysilicon (polycrystalline silicon). This strip of polysilicon, additionally to interconnecting the gates, is used to form the control gates of the memory cells.
FIG. 3
is an enlarged scale, schematic vertical cross-section view of a portion of a memory matrix, specifically a cell pair in a row. The cross-section in which the cell pair appear is taken at half-length of the polysilicon strip.
FIG. 3A
shows schematically the electric equivalent of FIG.
3
.
The polysilicon layer (Poly
2
) which comprises and connects the control gates is doped quite different from the underlying layer of polysilicon (Poly
1
) which provides the floating gate. By regarding the capacitive couplings between these conductive layers of Poly
1
and Poly
2
to be representative of capacitors with parallel planar plates separated by a dielectric layer of interpoly (FIG.
3
B), the parasitic capacitance that associates with each cell can be readily calculated at values lying typically somewhere between 0.2 and 0.4 fF per cell.
Resistivity per square of the layer Poly
2
is usually some ten Ohms. With the cell size and technological parameters being known factors, the time delay associated with the voltage rise across the wordline can now be calculated.
As an introductory approximation, a concentrated parameter model can be taken into consideration, with the time constant &tgr; associated with the row given as:
&tgr;
row
=R
cell
*C
cell
*N
cell
(1)
Assuming the row rise time to amount to no more than 10% of the overall access time, the maximum number of cells that can be connected to the same row can be calculated. The row time constant would usually be some ten nanoseconds.
The wordline voltage is therefore described by the following law:
V
row
=V
read
*(1
−e
−t/&tgr;row
) (2)
The problems connected with the operation of reading the contents of the memory cells will now be reviewed.
Shown in
FIG. 4
is a diagram of a conventional sense amplifier. The current flowed through a matrix cell and that through a reference cell are routed to a current/voltage I/V converter having outputs MAT and REF which represent the inputs to a final comparator operative to present the data in digital form.
The diode connection of P-channel transistors M
12
and M
13
in the I/V converter may be provided in either the matrix leg or the reference leg, as required. Gates NOR
1
and NOR
2
function, in combination with transistors M
14
and M
15
, to prevent “soft-writing” or spurious cell writing during a reading operation. These elements form a feed-back cascode type of arrangement which restrains the drain terminal of the cell from exceeding a potential of 1V. Transistors M
6
, M
7
and M
8
are used for column decoding in the matrix. The basic layout just described is added auxiliary circuitry for improved dynamic performance, i.e., reading speed, of the sense amplifier.
A primary task of the auxiliary circuitry is to equalize, i.e., short-circuit, the critical nodes of the converter, biasing them to an optimum value from the standpoint of switch-over speed.
FIG. 5
shows an example of equalizing circuitry. This circuitry is only active as a signal SAEQ is at a logic high, and does not alter the sense amplifier operation when the signal is in the other of its states. Transistor M
1
is operative to short-circuit the nodes MAT and REF directly. To obtain a perfectly even starting situation, the cascodes and drain nodes of the column decoders are usually equalized. Transistors M
1
and M
2
are low-threshold native transistors, while transistor M
3
is a thick-oxide transistor because the bitline node is applied a relatively high (4 to 5V) programming voltage Vp.
The equalizing step allows the nodes to be reset at each reading, bringing them to a convenient voltage value. Transistors M
4
and M
5
are to provide increased current duri
Crippa Luca
Micheloni Rino
de Guzman Dennis M.
Jorgenson Lisa K.
Le Vu A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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