Circuit and method for the erasure of a non-volatile and electri

Details Circuit and method for the erasure of a non-volatile and electri Circuit and method for the erasure of a non-volatile and electri

1997-11-26

2000-01-04

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 1134

Patent

active

060117249

ABSTRACT:
A method for the erasure of a non-volatile and electrically erasable memory in which the amplitude of the pulses that are sent to erase the memory varies as a function of the number of pulses previously sent. A circuit for the generation of erasure pulses of variable amplitude for a non-volatile and electrically erasable memory.

REFERENCES:
patent: 5475249 (1995-12-01), Watsuji et al.
patent: 5617359 (1997-04-01), Ninomiya
patent: 5619451 (1997-04-01), Costabello et al.
patent: 5724289 (1998-03-01), Watanabe
French Search Report from French application No. 9614777, filed Nov. 28, 1996.
An Improved Method for Programming a Word-Erasable EEPROM, Torelli et al., Alta Frequenza, vol. 52, No. 6, Nov. 1983, pp. 487-494.
Introduction to MOS LSI Design, Mayor et al., addison-wesley Pub. Co., Jun. 12, 1991 pp. 93-96 1983.

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