Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-01-30
2003-06-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230050, C365S194000, C365S189011
Reexamination Certificate
active
06580660
ABSTRACT:
BACKGROUND OF THE INVENTION
With the speeds of digital electronic circuit technology persistently increasing, problems involving signal synchronization have become more prevalent. Consider the situation of multiple parallel digital data paths, each of which consists of one or more digital data signals accompanied by an associated clock signal. Such multiple data paths may be the result of a single parallel data path that has been split, with each resulting path including a copy of the clock signal associated with the original data path. In many circuits, these multiple data paths may take different physical routes within a circuit. In such cases, a synchronization problem may arise between the multiple data paths if they are to be combined at some physical point in the circuit, assuming that the clock signals involved are all of substantially the same frequency. In other words, the signals of some of the data paths are likely to be shifted in time compared to the signals of other paths.
This phenomenon is depicted in the timing diagram of
FIG. 1
, wherein DATA
0
and DATA
1
are portions of the same original data path that have been split. CLK
0
and CLK
1
are copies of the clock originally associated with the digital data path prior to the data path being separated. Each segment of DATA
0
and DATA
1
in the figure, such as A
0
, B
0
, and the like, is a “sample,” which is the digital.state of the data signals associated with each clock pulse of CLK
0
and CLK
1
, respectively. As shown in
FIG. 1
, the various portions of the digital data path may be skewed by multiple clock cycles, causing a problem if the portions of the data path must be recombined. For example, A
0
and A
1
are samples of DATA
0
and DATA
1
that are desired to be synchronous; the same is true of B
0
and B
1
, C
0
and C
1
, and so on.
Several solutions to such synchronization problems have been utilized in the past. For instance, advancing or delaying the original clock signal would sometimes yield a point in time at which the all of the data was synchronized. However, in cases such as
FIG. 1
, in which portions of the data path are out of synchronization by multiple clock cycles, no such point in time at which synchronization may be achieved exists.
An alternate solution would be to add delay lines to some or all of the digital data signals in one or more data paths so that each data signal could be delayed varying amounts so that the resulting data paths ultimately could be synchronized. Unfortunately, no commercial electronic components are believed to be currently available which provide programmable multi-signal delay lines. Such parts could be produced in a custom manner, but would most likely be rather expensive to implement. Additionally, calibration of several programmable delay lines to find the optimum delay values for synchronization purposes may require an inordinate amount of time.
Another possibility is that the frequency of the clock signals involved could be reduced so that the timing differences between the various multiple data paths would be insignificant compared to the clock period, thereby eliminating any synchronization problems. Of course, such a solution is not ordinarily desirable due to the deleterious effect on the performance of the circuit.
Therefore, from the foregoing, a new circuit and method that allows for comparatively inexpensive and easily calibrated synchronization of multiple digital data paths would be advantageous.
SUMMARY OF THE INVENTION
Embodiments of the present invention, to be discussed in detail below, allow a circuit for synchronizing multiple digital data paths, each of which includes a set of digital data signals and an associated clock signal. The embodiments include a dual-port memory associated with each data path. Each memory is employed to store samples of each of the sets of digital data signals by way of the clock signal associated with that set of digital data signals. Each memory is also configured so that the samples stored in each of the memories is retrieved at a time such that each of the sets is synchronized with each other and with one of the clock signals.
Another embodiment of the invention takes the form of a method of synchronizing multiple digital data paths. Samples of each of the digital data signals from each of the paths are stored by way of the clock signal associated with that set of digital data signals. The samples of each set of digital data signals are then retrieved at a time such that each of the sets of digital data signals is synchronized with each other and with one of the clock signals.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4173007 (1979-10-01), McKeighen et al.
patent: 4374400 (1983-02-01), Holmes
patent: 4833651 (1989-05-01), Seltzer et al.
patent: 5825713 (1998-10-01), Lee
patent: 5956748 (1999-09-01), New
patent: 6473357 (2002-10-01), Fan et al.
Agilent Technologie,s Inc.
Way Kyle J.
Yoha Connie C.
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