Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-11-23
2001-08-28
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C345S100000, C345S182000
Reexamination Certificate
active
06282149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data communication circuits, and more particularly to a circuit and method for synchronizing data communication using a set of storage banks.
2. Description of the Related Art
Modem computer systems generally include one or more memory units such as random-access-memory (RAM), read-only-memory (ROM), FIFOs, etc. The memory units store data and instructions for use by a processor, which is coupled to the memory units via a memory bus. In communicating data and instructions, data capture devices such as toggle synchronizers are routinely used to synchronize communication between two devices having different data throughput rates. These data capture devices receive data from one device at one speed and store the data into FIFOs or register files. The stored data are then transmitted to the other device at a speed optimized for the latter device.
FIG. 1
shows a block diagram of a conventional computer system
100
including a processor
102
and a chip containing a memory device
104
. The chip containing the memory device
104
is coupled to the processor
102
and includes a buffer circuit
108
and a memory unit
114
. The memory unit
114
may be a random access memory (RAM) in the form of an internal register file. The buffer circuit
108
receives and buffers data for synchronized data transmission between the processor
102
and the memory unit
114
. To perform I/O operations, the processor
102
typically generates and transmits read/write control signals
112
(e.g., address, data, enable, etc.) to the chip with memory device
104
. For example, in read operations, the memory device
104
fetches data from the memory unit
114
and stores the data in the buffer circuit
108
. The requested data in the buffer circuit
108
are then transmitted to the processor
102
for processing.
In general, however, since the processor
102
can process data at a much faster rate than the memory device
104
is capable of operating, the memory device
104
often transmits a NOT_READY signal
110
to indicate that data is currently unavailable in the buffer circuit
108
. In response, the processor
102
stops initiating read/write operations and may perform other tasks while the NOT_READY signal
110
is asserted. When the requested data has been fetched into the buffer circuit
108
, the memory device
104
de-asserts the NOT_READY signal and provides the data to the processor
102
.
Unfortunately, however, the assertion of NOT_READY signals generally degrades performance of the computer system
100
by interrupting read/write operations. This is because the processor
102
must switch from performing one task to another task and then switch back to the original interrupted task when data becomes available. Furthermore, the interruption not only delays the interrupted read/write task but also all subsequent read/write operations. This means that the processor
104
is not efficiently utilized since the memory device
104
stops further read/write operations by the processor
102
until the interrupted read/write operation is completed. Thus, the interruption in such read/write operations may cause a bottleneck limiting the performance of high-speed successive read/write operations. By way of example, disk drive controllers
104
are often called upon by the processor
102
to perform many read/write operations to or from FIFOs. In such situations, interruptions in read/write operations delay the access of disk drive controller and thus slow down the response times of computer systems in general.
In view of the foregoing, there is a need for a circuit and method that can transmit data between devices having different data throughput rates without interruption.
SUMMARY OF THE INVENTION
The present invention fills this need by providing a method and a circuit for transmitting data between devices having different data throughput rates without interruption. The present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In accordance with a first aspect of the invention, the present invention provides a circuit for synchronizing data communication. The circuit includes enable circuitry, a set of storage banks, and synchronization circuitry. The storage banks receive and store data for transmission. The enable circuitry generates a set of enable signals to select a storage bank that has completed receiving the data for storage, i.e., FIFO, and to sequentially select the storage banks for transmitting the stored data. The synchronization circuitry synchronizes the selection of a storage bank to receive and store the data with the generation of the enable signals to transmit the stored data, wherein the synchronization circuitry selects the storage banks sequentially one after another. In this manner, the synchronization circuitry synchronizes the asynchronous READ strobe from a processor to a storage device.
In accordance with a second aspect of the invention, the present invention provides an interface circuit for synchronously transmitting data from a first device to a second device. The interface circuit includes a set of storage banks, a multiplexer, enable circuitry, and synchronization circuitry. The set of storage banks is configured to receive and store data with each storage bank being configured to transmit the stored data. The multiplexer is coupled to receive the stored data and a set of enable signals and selects a storage bank in response to the set of enable signals. In so doing, the multiplexer transmits the stored data for output. The enable circuitry is configured to generate the set of enable signals for sequentially selecting a storage bank that has completed receiving the data. The enable signals are used to sequentially select the storage banks for transmitting the stored data. The synchronization circuitry is configured to synchronize the selection of a storage bank to receive and store the data with the generation of the enable signals to transmit the stored data, wherein the synchronization circuitry selects the storage banks sequentially one after another.
In accordance with a third aspect of the invention, the present invention provides a method for synchronously transmitting data from a first device to a second device. The method includes (a) receiving and storing data in a set of storage banks, each storage bank including a plurality of storage cells, the storage banks being configured to transmit the stored data; (b) generating a set of enable signals to select a storage bank that has completed receiving the data for storage, the set of enable signals being adapted to sequentially select the storage banks for transmitting the stored data; (c) transmitting the stored data from the selected storage bank for output in response to the set of enable signals; and (d) sequentially synchronizing the selection of a storage bank to receive and store the data with the transmission of the stored data such that when one storage bank is receiving and storing the data, the stored data from another storage bank is transmitted.
Benefits and advantages of the present invention include a higher rate of data communication from the synchronizing the reception and transmission of data. In addition, the higher data transmission rate eliminates the need for generating and transmitting NOT_READY signals to the processor. This allows more efficient use of the processor by reducing wait states in transferring data. In contrast, in the case of a microprocessor reading from a chip that has a FIFO, conventional techniques have asserted NOT-READ signal between consecutive reads to allow the internal circuit to increment the pointers of the FIFO as a result of READ strobe being asserted and synchronized. Other advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by
Adaptec, Inc.
Le Vu A.
Martine & Penilla LLP
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