Circuit and method for symmetric asynchronous interface

Details Circuit and method for symmetric asynchronous interface Circuit and method for symmetric asynchronous interface

1999-07-28

2001-09-25

Chin, Wellington (Department: 2664)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

Reexamination Certificate

active

06295300

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a symmetric asynchronous interface circuit and a symmetric asynchronous interface method for executing handshaking procedure between two variable-clock devices which operate asynchronously.
DESCRIPTION OF THE PRIOR ART
Symmetric asynchronous interface circuits have been used for executing handshaking procedure between two devices which operate asynchronously. The term “asynchronous” means that the two devices connected by the interface circuit operate in sync with two different (independent) clock systems respectively. The term “symmetric” means that the interface circuit has a symmetric circuit composition so as to handle cases of both frequency relationships: (clock frequency
1
)≦(clock frequency
2
) and (clock frequency
1
)>(clock frequency
2
).
FIG. 1
shows a first example of a conventional symmetric asynchronous interface circuit, and
FIG. 2
shows the relationship between the clock frequency ratio and the overhead time ratio in the first conventional symmetric asynchronous interface circuit of FIG.
1
. The “clock frequency ratio” means a ratio between two clock frequencies of the two devices which are connected by the symmetric asynchronous interface circuit, and the “overhead time ratio” means the ratio of overhead time to the total time in the case where the first conventional symmetric asynchronous interface circuit of
FIG. 1
is employed. The “overhead time” means time necessary for executing the handshaking procedure between the two devices.
The first conventional symmetric asynchronous interface circuit shown in
FIG. 1
is a two-line interface circuit for handshaking READY signals (which are used for indicating completion of a basic operation such as an arithmetic logic operation, data preparation, etc.) between two devices. The two lines connect a first device control section FSM
1
(Finite State Machine
1
: a control section of a first device #
1
) and a second device control section FSM
2
(Finite State Machine
2
: a control section of a second device #
2
). In the first example, each of the control sections FSM
1
and FSM
2
is provided with a counter for counting to a predetermined number so as to determine the length of an active period of the READY signal. A fixed active period of the READY signal is preliminarily calculated with regard to the worst case of the clock frequency ratio, and a number corresponding to the fixed active period is set to the counter. In order to avoid malfunction, a READY signal of one device should not be activated until a READY signal of the other device becomes inactive, therefore, the counters are provided with idle states ST
14
and ST
24
which are shown in FIG.
1
.
FIGS. 3 through 6
show a second example of a conventional symmetric asynchronous interface circuit.
FIG. 3
is a circuit diagram of the second conventional symmetric asynchronous interface circuit, and
FIG. 4
is a schematic diagram showing the relationship between the clock frequency ratio and the overhead time ratio in the case of the second conventional symmetric asynchronous interface circuit of FIG.
3
.
FIG. 5
is a timing chart showing a case where the clock frequency ratio f(CK
1
)/f(CK
2
) is 2/3 and the duty ratio is 50%, and
FIG. 6
is a timing chart showing a case where the clock frequency ratio f(CK
1
)/f(CK
2
) is 1/1, the phase difference &thgr;(CK
2
)−&thgr;(CK
1
) is &pgr;, and the duty ratio is 50%.
The second conventional symmetric asynchronous interface circuit shown in
FIG. 3
is a four-line interface circuit employing two two-line handshakes, which handshakes not only the READY signal but also an ACKNOWLEDGE signal for dynamically controlling the active period of the READY signal. By the dynamic setting of the active period of the READY signal, limitations in the driving clock signal frequencies of the two devices are eliminated, and thus general versatility of the symmetric asynchronous interface circuit is increased. As shown in the relationship between the clock frequency ratio and the overhead time ratio in
FIG. 4
, the overhead time (ratio) in the case of the second conventional symmetric asynchronous interface circuit becomes constant regardless of the clock frequency ratio between the two devices, in contrast to the dotted line showing the case of the first conventional symmetric asynchronous interface circuit.
In the following, the operation of the second conventional symmetric asynchronous interface circuit will be described, taking a case where the two devices are provided with datapaths as an example and referring to the circuit diagram of
FIG. 3
, the timing chart of
FIG. 5
, and FIG.
7
through FIG.
9
.
FIG. 7
is a circuit diagram showing synchronization circuits SY
11
, SY
12
, SY
21
and SY
22
of the second conventional symmetric asynchronous interface circuit of FIG.
3
.
FIG. 8
is a circuit diagram showing a datapath DP
1
of the first device #
1
, and
FIG. 9
is a circuit diagram showing a datapath DP
2
of the second device #
2
. Incidentally, parts of the devices #
1
and #
2
except the first device control section FSM
1
and the second device control section FSM
2
are not shown in
FIG. 3
, and thus the datapath DP
1
of the device #
1
and the datapath DP
2
of the device #
2
are not shown in FIG.
3
. In the timing chart of
FIG. 5
, solid arrows indicate operations for transferring the right of control from the device #
1
to the device #
2
, and broken arrows indicate operations for transferring the control right from the device #
2
to the device #
1
. The following explanation will be given on the assumption that each cycle of the clock signal (CK
1
, CK
2
) ends at a rising edge, therefore, each clock cycle includes a falling edge and a rising edge after the falling edge. In this example, each device (#
1
/#
2
) is a circuit which executes increment of a count register (RG
11
/RG
21
) of its datapath (DP
1
/DP
2
) by 1 twice per one switching of the control right.
1. After an enough reset period, the first device control section FSM
1
(Finite State Machine
1
(the control section of the first device #
1
)) is in an initial state ST
10
, and a register RG
11
of the datapath DP
1
shown in
FIG. 8
holds a value 0.
2. Meanwhile, the second device control section FSM
2
((Finite State Machine
2
(the control section of the second device #
2
)) is in an initial state ST
22
, and a register RG
21
of the datapath DP
2
shown in
FIG. 9
holds a value 0.
3. In the first cycle of the clock signal (CK
1
) of the first device #
1
, the value (0) which has been held by the count register RG
11
shown in
FIG. 8
is incremented by 1, and the incremented value (1) is written in the count register RG
11
.
4. At the same time, the first device control section FSM
1
changes into the next state ST
13
.
5. In the second cycle of the clock signal (CK
1
), the value (1) which has been held by the count register RG
11
shown in
FIG. 8
is further incremented by 1, and the incremented value (2) is written in the count register RG
11
. At this point, procedure on the side of the first device #
1
is ended.
6. The first device control section FSM
1
can change into a state ST
11
for informing the second device #
2
that the procedure of the first device #
1
has been finished (i.e. that the first device #
1
is ready), if a signal RD
22
is inactive (0). In the example of
FIG. 5
, the signal RD
22
is inactive, and thus the first device control section FSM
1
can change into the state ST
11
.
7. In the third cycle of the clock signal (CK
1
), the first device control section FSM
1
changes into the state ST
11
, and thereby a signal RD
11
(a READY signal) for indicating the readiness of the first device #
1
is changed into active (1).
8. In the fourth cycle of the clock signal (CK
2
) of the second device #
2
, a D-FF (DF
111
) of the synchronization circuit SY
11
shown in
FIG. 7
latches the activated signal RD
11
in sync with a f

Affiliated with

Also associated with

Rating

Circuit and method for symmetric asynchronous interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for symmetric asynchronous interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for symmetric asynchronous interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2532101